riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-01-20	target/riscv: Remove helper_set_rod_rounding_mode	Richard Henderson	3	-10/+0
2023-01-20	target/riscv: Introduce helper_set_rounding_mode_chkfrm	Richard Henderson	4	-20/+61
2023-01-20	target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1	Andrew Bresticker	1	-0/+6
2023-01-20	target/riscv: Fix up masking of vsip/vsie accesses	Andrew Bresticker	1	-24/+11
2023-01-20	target/riscv: Use TARGET_FMT_lx for env->mhartid	Bin Meng	1	-3/+3
2023-01-20	target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()	Daniel Henrique Barboza	1	-194/+205
2023-01-20	target/riscv/cpu: set cpu->cfg in register_cpu_props()	Daniel Henrique Barboza	2	-0/+44
2023-01-20	target/riscv/cpu.c: Fix elen check	Dongxue Zhang	1	-1/+1
2023-01-20	hw/char: riscv_htif: Move registers from CPUArchState to HTIFState	Bin Meng	2	-8/+2
2023-01-18	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	Philippe Mathieu-Daudé	2	-6/+6
2023-01-06	Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...	Peter Maydell	18	-108/+874
2023-01-06	RISC-V: Add Zawrs ISA extension support	Christoph Muellner	5	-0/+64
2023-01-06	target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+	Bin Meng	1	-0/+6
2023-01-06	target/riscv: Simplify helper_sret() a little bit	Bin Meng	1	-14/+6
2023-01-06	target/riscv: Set pc_succ_insn for !rvc illegal insn	Richard Henderson	1	-8/+4
2023-01-06	target/riscv: Fix mret exception cause when no pmp rule is configured	Bin Meng	1	-1/+1
2023-01-06	target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()	Bin Meng	1	-0/+4
2023-01-06	target/riscv: support cache-related PMU events in virtual mode	Jim Shu	1	-1/+1
2023-01-06	target/riscv: Typo fix in sstc() predicate	Anup Patel	1	-1/+1
2023-01-06	target/riscv: Add itrigger_enabled field to CPURISCVState	LIU Zhiwei	4	-2/+20
2023-01-06	target/riscv: Enable native debug itrigger	LIU Zhiwei	1	-0/+72
2023-01-06	target/riscv: Add itrigger support when icount is enabled	LIU Zhiwei	4	-0/+65
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei	9	-11/+131
2023-01-06	target/riscv: generate virtual instruction exception	Mayuresh Chitale	1	-1/+7
2023-01-06	target/riscv: smstateen check for h/s/envcfg	Mayuresh Chitale	1	-7/+80
2023-01-06	target/riscv: Add smstateen support	Mayuresh Chitale	4	-0/+378
2023-01-06	target/riscv: Fix PMP propagation for tlb	LIU Zhiwei	3	-70/+42
2023-01-04	target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mip	Richard Henderson	1	-9/+1
2022-12-16	target/riscv: Convert to 3-phase reset	Peter Maydell	2	-6/+10
2022-12-14	cleanup: Tweak and re-run return_directly.cocci	Markus Armbruster	2	-25/+9
2022-10-26	Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into staging	Stefan Hajnoczi	1	-2/+7
2022-10-26	target/riscv: Convert to tcg_ops restore_state_to_opc	Richard Henderson	1	-2/+7
2022-10-24	treewide: Remove the unnecessary space before semicolon	Bin Meng	1	-1/+1
2022-10-14	target/riscv: pmp: Fixup TLB size calculation	Alistair Francis	1	-0/+12
2022-10-13	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Stefan Hajnoczi	1	-0/+4
2022-10-10	kvm: allow target-specific accelerator properties	Paolo Bonzini	1	-0/+4
2022-10-06	dump: Replace opaque DumpState pointer with a typed one	Janosch Frank	2	-6/+4
2022-10-04	accel/tcg: Introduce tb_pc and log_pc	Richard Henderson	1	-2/+2
2022-10-04	hw/core: Add CPUClass.get_pc	Richard Henderson	1	-0/+13
2022-09-27	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	Yang Liu	4	-15/+31
2022-09-27	target/riscv: rvv-1.0: Simplify vfwredsum code	Yang Liu	1	-46/+10
2022-09-27	target/riscv: debug: Add initial support of type 6 trigger	Frank Chang	2	-4/+188
2022-09-27	target/riscv: debug: Check VU/VS modes for type 2 trigger	Frank Chang	1	-0/+10
2022-09-27	target/riscv: debug: Create common trigger actions function	Frank Chang	2	-2/+70
2022-09-27	target/riscv: debug: Introduce tinfo CSR	Frank Chang	4	-3/+18
2022-09-27	target/riscv: debug: Restrict the range of tselect value can be written	Frank Chang	1	-6/+3
2022-09-27	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	Frank Chang	4	-88/+48
2022-09-27	target/riscv: debug: Introduce build_tdata1() to build tdata1 register content	Frank Chang	2	-5/+12
2022-09-27	target/riscv: debug: Determine the trigger type from tdata1.type	Frank Chang	5	-67/+140
2022-09-27	target/riscv: Check the correct exception cause in vector GDB stub	Frank Chang	1	-2/+2