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| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2022-10-16 18:17:24 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | fb3f3730e405e2451dffc03c572037c2e0bd44c0 (patch) | |
| tree | 7a1b49daf2d8e8e409cb08f258ebccc911004e43 /target/riscv | |
| parent | 252b06f638cdc79aa6dc33e91174b276eb69b3e0 (diff) | |
| download | qemu-fb3f3730e405e2451dffc03c572037c2e0bd44c0.zip qemu-fb3f3730e405e2451dffc03c572037c2e0bd44c0.tar.gz qemu-fb3f3730e405e2451dffc03c572037c2e0bd44c0.tar.bz2 | |
target/riscv: generate virtual instruction exception
This patch adds a mechanism to generate a virtual instruction
instruction exception instead of an illegal instruction exception
during instruction decode when virt is enabled.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221016124726.102129-4-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/translate.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index db123da..8b0bd38 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -76,6 +76,7 @@ typedef struct DisasContext { to reset this known value. */ int frm; RISCVMXL ol; + bool virt_inst_excp; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; bool hlsx; @@ -243,7 +244,11 @@ static void gen_exception_illegal(DisasContext *ctx) { tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, offsetof(CPURISCVState, bins)); - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + if (ctx->virt_inst_excp) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } } static void gen_exception_inst_addr_mis(DisasContext *ctx) @@ -1062,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; + ctx->virt_inst_excp = false; /* Check for compressed insn */ if (insn_len(opcode) == 2) { if (!has_ext(ctx, RVC)) { |