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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2022-12-06 16:20:51 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-02-27 22:29:01 +0100 |
| commit | 6d2d454a884eeae588a9a08fcbdc6c9b6d079720 (patch) | |
| tree | 0f9a78d52a0a1a1f81d6a97c99678c9c716af760 /target/riscv | |
| parent | 55b5b8e9284147529fa92804127f6d99ce4f89d9 (diff) | |
| download | qemu-6d2d454a884eeae588a9a08fcbdc6c9b6d079720.zip qemu-6d2d454a884eeae588a9a08fcbdc6c9b6d079720.tar.gz qemu-6d2d454a884eeae588a9a08fcbdc6c9b6d079720.tar.bz2 | |
target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu
The 'hwaddr' type is only available / meaningful on system emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216215519.5522-5-philmd@linaro.org>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7128438..df9cbc0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -573,7 +573,6 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -592,6 +591,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY +hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); |