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AgeCommit message (Expand)AuthorFilesLines
2019-03-19RISC-V: Convert trap debugging to trace eventsMichael Clark2-9/+5
2019-03-19RISC-V: Add support for vectored interruptsMichael Clark2-97/+60
2019-03-19RISC-V: Change local interrupts from edge to levelMichael Clark1-2/+2
2019-03-19RISC-V: linux-user support for RVE ABIKito Cheng2-1/+6
2019-03-19RISC-V: Allow interrupt controllers to claim interruptsMichael Clark3-8/+15
2019-03-19riscv: pmp: Log pmp access errors as guest errorsAlistair Francis1-7/+13
2019-03-19RISC-V: Add hooks to use the gdb xml files.Jim Wilson3-12/+349
2019-03-19RISC-V: Add debug support for accessing CSRs.Jim Wilson2-7/+30
2019-03-19RISC-V: Fixes to CSR_* register macros.Jim Wilson1-2/+33
2019-03-17target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann1-5/+25
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann1-20/+1
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann1-34/+0
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann3-18/+18
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2-211/+164
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2-71/+81
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann3-30/+34
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann3-100/+108
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2-11/+24
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2-16/+25
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2-60/+33
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann2-39/+27
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann3-81/+134
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann3-117/+195
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann4-38/+154
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann3-56/+126
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann3-600/+91
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann3-0/+389
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann2-0/+66
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann3-0/+415
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann3-144/+71
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann3-0/+178
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann4-9/+137
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann3-42/+88
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann3-12/+21
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann4-9/+206
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann4-10/+50
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2-0/+58
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann3-11/+69
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann4-14/+92
2019-02-11target/riscv: fix counter-enable checks in ctr()Xi Wang1-3/+9
2019-02-11RISC-V: Add misa runtime write supportMichael Clark4-3/+68
2019-02-11RISC-V: Add misa.MAFD checks to translateMichael Clark1-0/+158
2019-02-11RISC-V: Add misa to DisasContextMichael Clark1-35/+40
2019-02-11RISC-V: Add priv_ver to DisasContextAlistair Francis1-2/+5
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark5-37/+36
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark2-8/+34
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson2-13/+39
2019-02-11RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2-8/+8
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark4-79/+105
2019-01-09RISC-V: Implement atomic mip/sip CSR updatesMichael Clark1-28/+28
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