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2023-12-04
target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr
Daniel Henrique Barboza
1
-10
/
+9
2023-11-22
target/riscv/cpu_helper.c: Fix mxr bit behavior
Ivan Klokov
1
-4
/
+20
2023-11-22
target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
Ivan Klokov
1
-23
/
+7
2023-11-22
target/riscv: don't verify ISA compatibility for zicntr and zihpm
Clément Chigot
1
-0
/
+9
2023-11-15
target/riscv/cpu.h: spelling fix: separatly
Michael Tokarev
1
-2
/
+2
2023-11-07
hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()
Philippe Mathieu-Daudé
1
-2
/
+1
2023-11-07
target: Move ArchCPUClass definition to 'cpu.h'
Philippe Mathieu-Daudé
2
-16
/
+16
2023-11-07
target/riscv: Use env_archcpu() in [check_]nanbox()
Philippe Mathieu-Daudé
1
-4
/
+4
2023-11-07
target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'
Philippe Mathieu-Daudé
2
-7
/
+7
2023-11-07
target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
Philippe Mathieu-Daudé
2
-1
/
+2
2023-11-07
target: Unify QOM style
Philippe Mathieu-Daudé
2
-4
/
+1
2023-11-07
target/riscv: Add "pmu-mask" property to replace "pmu-num"
Rob Bradford
5
-12
/
+51
2023-11-07
target/riscv: Use existing PMU counter mask in FDT generation
Rob Bradford
2
-6
/
+2
2023-11-07
target/riscv: Don't assume PMU counters are continuous
Rob Bradford
1
-2
/
+3
2023-11-07
target/riscv: Propagate error from PMU setup
Rob Bradford
3
-12
/
+18
2023-11-07
target/riscv: cpu: Set the OpenTitan priv to 1.12.0
Alistair Francis
1
-1
/
+1
2023-11-07
target/riscv: Move vector crypto extensions to riscv_cpu_extensions
Max Chou
1
-18
/
+18
2023-11-07
target/riscv: Expose Zvks[c|g] extnesion properties
Max Chou
1
-0
/
+6
2023-11-07
target/riscv: Add cfg properties for Zvks[c|g] extensions
Max Chou
2
-0
/
+20
2023-11-07
target/riscv: Expose Zvkn[c|g] extnesion properties
Max Chou
1
-0
/
+6
2023-11-07
target/riscv: Add cfg properties for Zvkn[c|g] extensions
Max Chou
2
-0
/
+23
2023-11-07
target/riscv: Expose Zvkb extension property
Max Chou
1
-0
/
+2
2023-11-07
target/riscv: Replace Zvbb checking by Zvkb
Max Chou
1
-13
/
+24
2023-11-07
target/riscv: Add cfg property for Zvkb extension
Max Chou
2
-3
/
+4
2023-11-07
target/riscv: Expose Zvkt extension property
Max Chou
1
-0
/
+2
2023-11-07
target/riscv: Add cfg property for Zvkt extension
Max Chou
2
-0
/
+6
2023-11-07
target/riscv: correct csr_ops[CSR_MSECCFG]
Heinrich Schuchardt
1
-2
/
+5
2023-11-07
target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot
Daniel Henrique Barboza
1
-0
/
+5
2023-11-07
target/riscv/kvm: add zihpm reg
Daniel Henrique Barboza
1
-0
/
+1
2023-11-07
target/riscv: add zihpm extension flag for TCG
Daniel Henrique Barboza
3
-0
/
+17
2023-11-07
target/riscv/kvm: add zicntr reg
Daniel Henrique Barboza
1
-0
/
+1
2023-11-07
target/riscv: add zicntr extension flag for TCG
Daniel Henrique Barboza
4
-0
/
+25
2023-11-07
target/riscv: pmp: Ignore writes when RW=01
Mayuresh Chitale
1
-0
/
+5
2023-11-07
target/riscv: pmp: Clear pmp/smepmp bits on reset
Mayuresh Chitale
3
-0
/
+23
2023-11-07
Add epmp to extensions list and rename it to smepmp
Himanshu Chauhan
5
-17
/
+15
2023-11-07
target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion
Daniel Henrique Barboza
1
-0
/
+20
2023-11-07
target/riscv: add riscv_cpu_accelerator_compatible()
Daniel Henrique Barboza
4
-1
/
+17
2023-11-07
target/riscv: handle custom props in qmp_query_cpu_model_expansion
Daniel Henrique Barboza
1
-0
/
+65
2023-11-07
target/riscv/tcg: add tcg_cpu_finalize_features()
Daniel Henrique Barboza
4
-30
/
+53
2023-11-07
qapi,risc-v: add query-cpu-model-expansion
Daniel Henrique Barboza
1
-0
/
+75
2023-11-07
target/riscv/kvm/kvm-cpu.c: add missing property getters()
Daniel Henrique Barboza
1
-3
/
+37
2023-11-07
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
Rajnesh Kanwal
5
-32
/
+236
2023-11-07
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
Rajnesh Kanwal
6
-38
/
+291
2023-11-07
target/riscv: Split interrupt logic from riscv_cpu_update_mip.
Rajnesh Kanwal
2
-7
/
+19
2023-11-07
target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
Rajnesh Kanwal
1
-1
/
+6
2023-11-07
target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
Rajnesh Kanwal
1
-6
/
+4
2023-11-07
target/riscv: Without H-mode mask all HS mode inturrupts in mie.
Rajnesh Kanwal
1
-1
/
+1
2023-11-07
target/riscv: rename ext_icboz to ext_zicboz
Daniel Henrique Barboza
4
-11
/
+11
2023-11-07
target/riscv: rename ext_icbom to ext_zicbom
Daniel Henrique Barboza
4
-11
/
+11
2023-11-07
target/riscv: rename ext_icsr to ext_zicsr
Daniel Henrique Barboza
5
-21
/
+21
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