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2023-12-04target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csrDaniel Henrique Barboza1-10/+9
2023-11-22target/riscv/cpu_helper.c: Fix mxr bit behaviorIvan Klokov1-4/+20
2023-11-22target/riscv/cpu_helper.c: Invalid exception on MMU translation stageIvan Klokov1-23/+7
2023-11-22target/riscv: don't verify ISA compatibility for zicntr and zihpmClément Chigot1-0/+9
2023-11-15target/riscv/cpu.h: spelling fix: separatlyMichael Tokarev1-2/+2
2023-11-07hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()Philippe Mathieu-Daudé1-2/+1
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé2-16/+16
2023-11-07target/riscv: Use env_archcpu() in [check_]nanbox()Philippe Mathieu-Daudé1-4/+4
2023-11-07target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'Philippe Mathieu-Daudé2-7/+7
2023-11-07target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'Philippe Mathieu-Daudé2-1/+2
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé2-4/+1
2023-11-07target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford5-12/+51
2023-11-07target/riscv: Use existing PMU counter mask in FDT generationRob Bradford2-6/+2
2023-11-07target/riscv: Don't assume PMU counters are continuousRob Bradford1-2/+3
2023-11-07target/riscv: Propagate error from PMU setupRob Bradford3-12/+18
2023-11-07target/riscv: cpu: Set the OpenTitan priv to 1.12.0Alistair Francis1-1/+1
2023-11-07target/riscv: Move vector crypto extensions to riscv_cpu_extensionsMax Chou1-18/+18
2023-11-07target/riscv: Expose Zvks[c|g] extnesion propertiesMax Chou1-0/+6
2023-11-07target/riscv: Add cfg properties for Zvks[c|g] extensionsMax Chou2-0/+20
2023-11-07target/riscv: Expose Zvkn[c|g] extnesion propertiesMax Chou1-0/+6
2023-11-07target/riscv: Add cfg properties for Zvkn[c|g] extensionsMax Chou2-0/+23
2023-11-07target/riscv: Expose Zvkb extension propertyMax Chou1-0/+2
2023-11-07target/riscv: Replace Zvbb checking by ZvkbMax Chou1-13/+24
2023-11-07target/riscv: Add cfg property for Zvkb extensionMax Chou2-3/+4
2023-11-07target/riscv: Expose Zvkt extension propertyMax Chou1-0/+2
2023-11-07target/riscv: Add cfg property for Zvkt extensionMax Chou2-0/+6
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt1-2/+5
2023-11-07target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapotDaniel Henrique Barboza1-0/+5
2023-11-07target/riscv/kvm: add zihpm regDaniel Henrique Barboza1-0/+1
2023-11-07target/riscv: add zihpm extension flag for TCGDaniel Henrique Barboza3-0/+17
2023-11-07target/riscv/kvm: add zicntr regDaniel Henrique Barboza1-0/+1
2023-11-07target/riscv: add zicntr extension flag for TCGDaniel Henrique Barboza4-0/+25
2023-11-07target/riscv: pmp: Ignore writes when RW=01Mayuresh Chitale1-0/+5
2023-11-07target/riscv: pmp: Clear pmp/smepmp bits on resetMayuresh Chitale3-0/+23
2023-11-07Add epmp to extensions list and rename it to smepmpHimanshu Chauhan5-17/+15
2023-11-07target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansionDaniel Henrique Barboza1-0/+20
2023-11-07target/riscv: add riscv_cpu_accelerator_compatible()Daniel Henrique Barboza4-1/+17
2023-11-07target/riscv: handle custom props in qmp_query_cpu_model_expansionDaniel Henrique Barboza1-0/+65
2023-11-07target/riscv/tcg: add tcg_cpu_finalize_features()Daniel Henrique Barboza4-30/+53
2023-11-07qapi,risc-v: add query-cpu-model-expansionDaniel Henrique Barboza1-0/+75
2023-11-07target/riscv/kvm/kvm-cpu.c: add missing property getters()Daniel Henrique Barboza1-3/+37
2023-11-07target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal5-32/+236
2023-11-07target/riscv: Add M-mode virtual interrupt and IRQ filtering support.Rajnesh Kanwal6-38/+291
2023-11-07target/riscv: Split interrupt logic from riscv_cpu_update_mip.Rajnesh Kanwal2-7/+19
2023-11-07target/riscv: Set VS* bits to one in mideleg when H-Ext is enabledRajnesh Kanwal1-1/+6
2023-11-07target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.Rajnesh Kanwal1-6/+4
2023-11-07target/riscv: Without H-mode mask all HS mode inturrupts in mie.Rajnesh Kanwal1-1/+1
2023-11-07target/riscv: rename ext_icboz to ext_zicbozDaniel Henrique Barboza4-11/+11
2023-11-07target/riscv: rename ext_icbom to ext_zicbomDaniel Henrique Barboza4-11/+11
2023-11-07target/riscv: rename ext_icsr to ext_zicsrDaniel Henrique Barboza5-21/+21
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