diff options
author | Rob Bradford <rbradford@rivosinc.com> | 2023-10-31 15:37:14 +0000 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:06:02 +1000 |
commit | 7c1bb1d8d412f03ec7d6042971892bd0dff222b7 (patch) | |
tree | 0a65655e0080a9fc1d9f0e502bff427e3733d587 /target/riscv | |
parent | 755b41d09f516109f5ddc49aae86358c72e656d5 (diff) | |
download | qemu-7c1bb1d8d412f03ec7d6042971892bd0dff222b7.zip qemu-7c1bb1d8d412f03ec7d6042971892bd0dff222b7.tar.gz qemu-7c1bb1d8d412f03ec7d6042971892bd0dff222b7.tar.bz2 |
target/riscv: Don't assume PMU counters are continuous
Check the PMU available bitmask when checking if a counter is valid
rather than comparing the index against the number of PMUs.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20231031154000.18134-3-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/csr.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fc26b52..fde7ce1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -188,7 +188,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { - int pmu_num = riscv_cpu_cfg(env)->pmu_num; + RISCVCPU *cpu = env_archcpu(env); + uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs; int ctr_index; int base_csrno = CSR_MHPMCOUNTER3; @@ -197,7 +198,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; - if (!pmu_num || ctr_index >= pmu_num) { + if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) { /* The PMU is not enabled or counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } |