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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis1-1/+1
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+6
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+32
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+6
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+28
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng1-0/+36
2021-06-08target/riscv: rvb: shift onesKito Cheng1-0/+14
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang1-0/+61
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang1-0/+39
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng1-0/+40
2021-06-08target/riscv: rvb: count bits setFrank Chang1-0/+6
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-0/+38
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis1-3/+6
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis1-2/+17
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra1-2/+2
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer1-178/+1
2021-01-18riscv: Add semihosting supportKeith Packard1-0/+11
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis1-0/+2
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis1-10/+0
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson1-0/+18
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson1-0/+11
2020-08-21meson: targetPaolo Bonzini1-2/+2
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini1-10/+10
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei1-0/+7
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei1-2/+15
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei1-1/+2
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis1-0/+1
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis1-1/+1
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis1-1/+15
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis1-0/+13
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis1-0/+8
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée1-19/+21
2020-01-24Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...Peter Maydell1-1/+1
2020-01-16target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung1-1/+1
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-11-14remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata1-3/+1
2019-10-28target/riscv: fetch code with translator_ldEmilio G. Cota1-1/+1
2019-08-19target/riscv: Remove redundant declaration pragmasRichard Henderson1-18/+1
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt1-0/+3
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson1-2/+17
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson1-1/+0
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson1-0/+6
2019-05-24target/riscv: Use --static-decode for decodetreeRichard Henderson1-3/+0
2019-05-24target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson1-0/+18
2019-05-24RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau1-5/+25
2019-05-06decodetree: Add DisasContext argument to !function expandersRichard Henderson1-2/+2
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt1-0/+21
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann1-20/+1
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