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translate.c
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3 days
target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
LIU Zhiwei
1
-0
/
+13
3 days
target/riscv: Add AMO instructions for Zabha
LIU Zhiwei
1
-1
/
+3
3 days
target/riscv: Move gen_amo before implement Zabha
LIU Zhiwei
1
-0
/
+21
3 days
target/riscv: Add zcmop extension
LIU Zhiwei
1
-0
/
+1
3 days
target/riscv: Add zimop extension
LIU Zhiwei
1
-0
/
+1
2024-06-04
Merge tag 'hw-misc-accel-20240604' of https://github.com/philmd/qemu into sta...
Richard Henderson
1
-1
/
+0
2024-06-04
target/riscv: Remove unused 'instmap.h' header in translate.c
Philippe Mathieu-Daudé
1
-1
/
+0
2024-06-03
target/riscv: Implement dynamic establishment of custom decoder
Huang Tao
1
-16
/
+15
2024-05-15
target/riscv: Use translator_ld* for everything
Richard Henderson
1
-3
/
+3
2024-05-15
accel/tcg: Provide default implementation of disas_log
Richard Henderson
1
-18
/
+0
2024-04-09
target/riscv: Use insn_start from DisasContextBase
Richard Henderson
1
-6
/
+5
2024-03-22
target/riscv: enable 'vstart_eq_zero' in the end of insns
Ivan Klokov
1
-0
/
+6
2024-03-08
RISC-V: Add support for Ztso
Palmer Dabbelt
1
-0
/
+3
2024-02-09
target/riscv: Move misa_mxl_max to class
Akihiko Odaki
1
-1
/
+2
2024-01-29
target: Use vaddr in gen_intermediate_code
Anton Johansson
1
-1
/
+1
2024-01-10
target/riscv: Add support for Zacas extension
Weiwei Li
1
-0
/
+1
2023-10-04
accel/tcg: Replace CPUState.env_ptr with cpu_env()
Richard Henderson
1
-3
/
+3
2023-10-03
tcg: Rename cpu_env to tcg_env
Richard Henderson
1
-25
/
+25
2023-09-11
target/riscv: Add Zvbc ISA extension support
Lawrence Hunter
1
-0
/
+1
2023-07-10
riscv: Add support for the Zfa extension
Christoph Müllner
1
-0
/
+1
2023-07-10
target/riscv: Add support for Zfbfmin extension
Weiwei Li
1
-0
/
+1
2023-07-10
target/riscv: Add additional xlen for address when MPRV=1
Weiwei Li
1
-1
/
+12
2023-07-10
target/riscv: Factor out extension tests to cpu_cfg.h
Christoph Müllner
1
-25
/
+2
2023-06-13
target/riscv: Remove pc_succ_insn from DisasContext
Weiwei Li
1
-6
/
+1
2023-06-13
target/riscv: Enable PC-relative translation
Weiwei Li
1
-7
/
+40
2023-06-13
target/riscv: Use true diff for gen_pc_plus_diff
Weiwei Li
1
-7
/
+6
2023-06-13
target/riscv: Change gen_set_pc_imm to gen_update_pc
Weiwei Li
1
-5
/
+5
2023-06-13
target/riscv: Change gen_goto_tb to work on displacements
Weiwei Li
1
-3
/
+5
2023-06-13
target/riscv: Introduce cur_insn_len into DisasContext
Weiwei Li
1
-1
/
+3
2023-06-13
target/riscv: Fix target address to update badaddr
Weiwei Li
1
-11
/
+10
2023-06-13
target/riscv: Update check for Zca/Zcf/Zcd
Weiwei Li
1
-2
/
+3
2023-06-05
accel/tcg: Introduce translator_io_start
Richard Henderson
1
-2
/
+0
2023-06-05
tcg: Pass TCGHelperInfo to tcg_gen_callN
Richard Henderson
1
-0
/
+4
2023-05-05
target/riscv: Handle HLV, HSV via helpers
Richard Henderson
1
-2
/
+0
2023-05-05
target/riscv: Separate priv from mmu_idx
Fei Wu
1
-0
/
+2
2023-05-05
target/riscv: Add a tb flags field for vstart
LIU Zhiwei
1
-2
/
+2
2023-05-05
target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
Richard Henderson
1
-22
/
+10
2023-05-05
target/riscv: Encode the FS and VS on a normal way for tb flags
LIU Zhiwei
1
-18
/
+14
2023-05-05
target/riscv: Extract virt enabled state from tb flags
LIU Zhiwei
1
-9
/
+1
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
1
-8
/
+12
2023-05-05
target/riscv: Fix format for indentation
Weiwei Li
1
-2
/
+2
2023-05-05
target/riscv: Remove riscv_cpu_virt_enabled()
Weiwei Li
1
-1
/
+1
2023-05-05
target/riscv: Convert env->virt to a bool env->virt_enabled
LIU Zhiwei
1
-2
/
+2
2023-05-05
target/riscv: add support for Zcmp extension
Weiwei Li
1
-0
/
+5
2023-05-05
target/riscv: add support for Zcb extension
Weiwei Li
1
-0
/
+2
2023-05-05
target/riscv: add support for Zca extension
Weiwei Li
1
-2
/
+6
2023-03-07
Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...
Peter Maydell
1
-0
/
+1
2023-03-05
target/riscv: Avoid tcg_const_*
Richard Henderson
1
-2
/
+2
2023-03-05
target/riscv: Drop tcg_temp_free
Richard Henderson
1
-7
/
+0
2023-03-05
target/riscv: Drop temp_new
Richard Henderson
1
-24
/
+6
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