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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson1-2/+0
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu1-0/+2
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei1-2/+2
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson1-22/+10
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei1-18/+14
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei1-9/+1
2023-05-05target/riscv: Fix format for commentsWeiwei Li1-8/+12
2023-05-05target/riscv: Fix format for indentationWeiwei Li1-2/+2
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li1-1/+1
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei1-2/+2
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li1-0/+5
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li1-0/+2
2023-05-05target/riscv: add support for Zca extensionWeiwei Li1-2/+6
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell1-0/+1
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson1-2/+2
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson1-7/+0
2023-03-05target/riscv: Drop temp_newRichard Henderson1-24/+6
2023-03-05target/riscv: Drop ftemp_newRichard Henderson1-20/+4
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner1-0/+1
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell1-1/+2
2023-03-01target/riscv: Add support for Zicond extensionWeiwei Li1-0/+1
2023-03-01target/riscv: Fix checking of whether instruciton at 'pc_next' spans pagesShaobo Song1-1/+1
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta1-0/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner1-3/+3
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner1-1/+20
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner1-2/+2
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner1-1/+2
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner1-1/+1
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner1-0/+8
2023-01-20target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson1-4/+0
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson1-0/+19
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner1-0/+1
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson1-8/+4
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei1-3/+30
2023-01-06target/riscv: generate virtual instruction exceptionMayuresh Chitale1-1/+7
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell1-0/+1
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen1-0/+2
2022-09-07target/riscv: Fix typo and restore Pointer Masking functionality for RISC-VAlexey Baturo1-1/+1
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot1-2/+18
2022-09-06target/riscv: Make translator stop before the end of a pageRichard Henderson1-4/+13
2022-09-06target/riscv: Add MAX_INSN_LEN and insn_lenRichard Henderson1-1/+9
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+3
2022-07-03target/riscv: Minimize the calls to decode_save_opcRichard Henderson1-9/+9
2022-07-03target/riscv: Remove generate_exception_mtvalRichard Henderson1-9/+2
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