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path: root/target/riscv/translate.c
AgeCommit message (Expand)AuthorFilesLines
2019-10-28target/riscv: fetch code with translator_ldEmilio G. Cota1-1/+1
2019-08-19target/riscv: Remove redundant declaration pragmasRichard Henderson1-18/+1
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt1-0/+3
2019-05-24target/riscv: Split gen_arith_imm into functional and tempRichard Henderson1-2/+17
2019-05-24target/riscv: Split RVC32 and RVC64 insns into separate filesRichard Henderson1-1/+0
2019-05-24target/riscv: Merge argument decode for RVC shiftiRichard Henderson1-0/+6
2019-05-24target/riscv: Use --static-decode for decodetreeRichard Henderson1-3/+0
2019-05-24target/riscv: Name the argument sets for all of insn32 formatsRichard Henderson1-0/+18
2019-05-24RISC-V: fix single stepping over ret and other branching instructionsFabien Chouteau1-5/+25
2019-05-06decodetree: Add DisasContext argument to !function expandersRichard Henderson1-2/+2
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-03-22target/riscv: Zero extend the inputs of divuw and remuwPalmer Dabbelt1-0/+21
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann1-20/+1
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann1-34/+0
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann1-2/+2
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann1-187/+133
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann1-41/+18
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann1-15/+25
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann1-80/+27
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann1-3/+5
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann1-2/+4
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann1-47/+0
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann1-38/+0
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann1-81/+2
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann1-117/+1
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann1-37/+16
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann1-56/+1
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann1-600/+1
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann1-0/+1
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann1-0/+1
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann1-144/+0
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann1-0/+1
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann1-9/+7
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann1-42/+1
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann1-12/+0
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann1-9/+0
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann1-7/+0
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann1-11/+1
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann1-14/+17
2019-02-11RISC-V: Add misa.MAFD checks to translateMichael Clark1-0/+158
2019-02-11RISC-V: Add misa to DisasContextMichael Clark1-35/+40
2019-02-11RISC-V: Add priv_ver to DisasContextAlistair Francis1-2/+5
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson1-1/+39
2019-02-11RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson1-5/+5
2018-11-13RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt1-2/+0
2018-11-13target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann1-5/+13
2018-11-13target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann1-1/+3
2018-09-05target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota1-6/+1
2018-09-05target/riscv: optimize indirect branchesEmilio G. Cota1-1/+1
2018-09-05target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota1-1/+1
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