riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson	1	-2/+17
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson	1	-1/+0
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson	1	-0/+6
2019-05-24	target/riscv: Use --static-decode for decodetree	Richard Henderson	1	-3/+0
2019-05-24	target/riscv: Name the argument sets for all of insn32 formats	Richard Henderson	1	-0/+18
2019-05-24	RISC-V: fix single stepping over ret and other branching instructions	Fabien Chouteau	1	-5/+25
2019-05-06	decodetree: Add DisasContext argument to !function expanders	Richard Henderson	1	-2/+2
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson	1	-2/+2
2019-03-22	target/riscv: Zero extend the inputs of divuw and remuw	Palmer Dabbelt	1	-0/+21
2019-03-13	target/riscv: Remove decode_RV32_64G()	Bastian Koppelmann	1	-20/+1
2019-03-13	target/riscv: Remove gen_system()	Bastian Koppelmann	1	-34/+0
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann	1	-2/+2
2019-03-13	target/riscv: Remove manual decoding of RV32/64M insn	Bastian Koppelmann	1	-187/+133
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann	1	-41/+18
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann	1	-15/+25
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann	1	-80/+27
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann	1	-3/+5
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann	1	-2/+4
2019-03-13	target/riscv: Remove manual decoding from gen_branch()	Bastian Koppelmann	1	-47/+0
2019-03-13	target/riscv: Remove gen_jalr()	Bastian Koppelmann	1	-38/+0
2019-03-13	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	Bastian Koppelmann	1	-81/+2
2019-03-13	target/riscv: Convert quadrant 1 of RVXC insns to decodetree	Bastian Koppelmann	1	-117/+1
2019-03-13	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	Bastian Koppelmann	1	-37/+16
2019-03-13	target/riscv: Convert RV priv insns to decodetree	Bastian Koppelmann	1	-56/+1
2019-03-13	target/riscv: Convert RV64D insns to decodetree	Bastian Koppelmann	1	-600/+1
2019-03-13	target/riscv: Convert RV32D insns to decodetree	Bastian Koppelmann	1	-0/+1
2019-03-13	target/riscv: Convert RV32F insns to decodetree	Bastian Koppelmann	1	-0/+1
2019-03-13	target/riscv: Convert RV64A insns to decodetree	Bastian Koppelmann	1	-144/+0
2019-03-13	target/riscv: Convert RV32A insns to decodetree	Bastian Koppelmann	1	-0/+1
2019-03-13	target/riscv: Convert RVXM insns to decodetree	Bastian Koppelmann	1	-9/+7
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann	1	-42/+1
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann	1	-12/+0
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann	1	-9/+0
2019-03-13	target/riscv: Convert RV64I load/store insns to decodetree	Bastian Koppelmann	1	-7/+0
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann	1	-11/+1
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann	1	-14/+17
2019-02-11	RISC-V: Add misa.MAFD checks to translate	Michael Clark	1	-0/+158
2019-02-11	RISC-V: Add misa to DisasContext	Michael Clark	1	-35/+40
2019-02-11	RISC-V: Add priv_ver to DisasContext	Alistair Francis	1	-2/+5
2019-02-11	RISC-V: Mark mstatus.fs dirty	Richard Henderson	1	-1/+39
2019-02-11	RISC-V: Split out mstatus_fs from tb_flags	Richard Henderson	1	-5/+5
2018-11-13	RISC-V: Respect fences for user-only emulators	Palmer Dabbelt	1	-2/+0
2018-11-13	target/riscv: Fix sfence.vm/a both available in any priv version	Bastian Koppelmann	1	-5/+13
2018-11-13	target/riscv: Fix FCLASS_D being treated as RV64 only	Bastian Koppelmann	1	-1/+3
2018-09-05	target/riscv: call gen_goto_tb on DISAS_TOO_MANY	Emilio G. Cota	1	-6/+1
2018-09-05	target/riscv: optimize indirect branches	Emilio G. Cota	1	-1/+1
2018-09-05	target/riscv: optimize cross-page direct jumps in softmmu	Emilio G. Cota	1	-1/+1
2018-06-01	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson	1	-10/+10
2018-05-11	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...	Peter Maydell	1	-49/+17
2018-05-10	target/riscv: Use new atomic min/max expanders	Richard Henderson	1	-49/+17