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Author
Files
Lines
2020-08-25
target/riscv: Support the Virtual Instruction fault
Alistair Francis
1
-1
/
+1
2020-08-25
target/riscv: Allow generating hlv/hlvx/hsv instructions
Alistair Francis
1
-0
/
+340
2020-08-21
target/riscv: check before allocating TCG temps
LIU Zhiwei
2
-8
/
+8
2020-08-21
target/riscv: Clean up fmv.w.x
LIU Zhiwei
1
-5
/
+1
2020-08-21
target/riscv: Check nanboxed inputs in trans_rvf.inc.c
Richard Henderson
1
-16
/
+55
2020-08-21
target/riscv: Generate nanboxed results from trans_rvf.inc.c
Richard Henderson
1
-0
/
+4
2020-08-21
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Richard Henderson
1
-15
/
+1
2020-08-21
meson: rename included C source files to .c.inc
Paolo Bonzini
8
-0
/
+0
2020-07-22
target/riscv: fix vector index load/store constraints
LIU Zhiwei
1
-1
/
+9
2020-07-22
target/riscv: Quiet Coverity complains about vamo*
LIU Zhiwei
1
-0
/
+1
2020-07-13
target/riscv: fix return value of do_opivx_widen()
Frank Chang
1
-1
/
+1
2020-07-13
target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
Frank Chang
1
-1
/
+1
2020-07-13
target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
Frank Chang
1
-0
/
+5
2020-07-02
target/riscv: vector compress instruction
LIU Zhiwei
1
-0
/
+32
2020-07-02
target/riscv: vector register gather instruction
LIU Zhiwei
1
-0
/
+78
2020-07-02
target/riscv: vector slide instructions
LIU Zhiwei
1
-0
/
+18
2020-07-02
target/riscv: floating-point scalar move instructions
LIU Zhiwei
1
-0
/
+49
2020-07-02
target/riscv: integer scalar move instruction
LIU Zhiwei
1
-0
/
+60
2020-07-02
target/riscv: integer extract instruction
LIU Zhiwei
1
-0
/
+116
2020-07-02
target/riscv: vector element index instruction
LIU Zhiwei
1
-0
/
+25
2020-07-02
target/riscv: vector iota instruction
LIU Zhiwei
1
-0
/
+27
2020-07-02
target/riscv: set-X-first mask bit
LIU Zhiwei
1
-0
/
+28
2020-07-02
target/riscv: vmfirst find-first-set mask bit
LIU Zhiwei
1
-0
/
+32
2020-07-02
target/riscv: vector mask population count vmpopc
LIU Zhiwei
1
-0
/
+32
2020-07-02
target/riscv: vector mask-register logical instructions
LIU Zhiwei
1
-0
/
+35
2020-07-02
target/riscv: vector widening floating-point reduction instructions
LIU Zhiwei
1
-0
/
+3
2020-07-02
target/riscv: vector single-width floating-point reduction instructions
LIU Zhiwei
1
-0
/
+5
2020-07-02
target/riscv: vector wideing integer reduction instructions
LIU Zhiwei
1
-0
/
+4
2020-07-02
target/riscv: vector single-width integer reduction instructions
LIU Zhiwei
1
-0
/
+18
2020-07-02
target/riscv: narrowing floating-point/integer type-convert instructions
LIU Zhiwei
1
-0
/
+48
2020-07-02
target/riscv: widening floating-point/integer type-convert instructions
LIU Zhiwei
1
-0
/
+48
2020-07-02
target/riscv: vector floating-point/integer type-convert instructions
LIU Zhiwei
1
-0
/
+6
2020-07-02
target/riscv: vector floating-point merge instructions
LIU Zhiwei
1
-0
/
+38
2020-07-02
target/riscv: vector floating-point classify instructions
LIU Zhiwei
1
-0
/
+3
2020-07-02
target/riscv: vector floating-point compare instructions
LIU Zhiwei
1
-0
/
+35
2020-07-02
target/riscv: vector floating-point sign-injection instructions
LIU Zhiwei
1
-0
/
+8
2020-07-02
target/riscv: vector floating-point min/max instructions
LIU Zhiwei
1
-0
/
+6
2020-07-02
target/riscv: vector floating-point square-root instruction
LIU Zhiwei
1
-0
/
+43
2020-07-02
target/riscv: vector widening floating-point fused multiply-add instructions
LIU Zhiwei
1
-0
/
+10
2020-07-02
target/riscv: vector single-width floating-point fused multiply-add instructions
LIU Zhiwei
1
-0
/
+18
2020-07-02
target/riscv: vector widening floating-point multiply
LIU Zhiwei
1
-0
/
+4
2020-07-02
target/riscv: vector single-width floating-point multiply/divide instructions
LIU Zhiwei
1
-0
/
+7
2020-07-02
target/riscv: vector widening floating-point add/subtract instructions
LIU Zhiwei
1
-0
/
+149
2020-07-02
target/riscv: vector single-width floating-point add/subtract instructions
LIU Zhiwei
1
-0
/
+118
2020-07-02
target/riscv: vector narrowing fixed-point clip instructions
LIU Zhiwei
1
-0
/
+8
2020-07-02
target/riscv: vector single-width scaling shift instructions
LIU Zhiwei
1
-0
/
+8
2020-07-02
target/riscv: vector widening saturating scaled multiply-add
LIU Zhiwei
1
-0
/
+9
2020-07-02
target/riscv: vector single-width fractional multiply with rounding and satur...
LIU Zhiwei
1
-0
/
+4
2020-07-02
target/riscv: vector single-width averaging add and subtract
LIU Zhiwei
1
-0
/
+7
2020-07-02
target/riscv: vector single-width saturating add and subtract
LIU Zhiwei
1
-0
/
+16
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