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AgeCommit message (Expand)AuthorFilesLines
2021-10-22target/riscv: Fix orc.b implementationPhilipp Tomsich1-5/+8
2021-10-22target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang1-1/+2
2021-10-15target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson3-8/+6
2021-10-15target/riscv: Remove dead code after exceptionRichard Henderson1-5/+1
2021-10-07target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich1-72/+14
2021-10-07target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich1-32/+8
2021-10-07target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich1-22/+17
2021-10-07target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich1-22/+29
2021-10-07target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich1-1/+31
2021-10-07target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich1-10/+15
2021-10-07target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich1-70/+0
2021-10-07target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich1-56/+0
2021-10-07target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich1-5/+11
2021-10-07target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich1-3/+5
2021-10-07target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich1-1/+1
2021-10-07target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich1-2/+4
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson1-53/+21
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson1-210/+56
2021-09-01target/riscv: Use {get,dest}_gpr for RVDRichard Henderson1-65/+60
2021-09-01target/riscv: Use {get,dest}_gpr for RVFRichard Henderson1-76/+70
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson1-13/+6
2021-09-01target/riscv: Use {get,dest}_gpr for RVARichard Henderson1-28/+19
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson1-52/+122
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson1-18/+20
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson1-15/+10
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson1-2/+12
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson2-140/+77
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson1-15/+9
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson1-0/+234
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson1-0/+127
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson1-22/+18
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson1-8/+8
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson3-40/+45
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson8-115/+115
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson2-44/+24
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+26
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+24
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+26
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+31
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng1-0/+39
2021-06-08target/riscv: rvb: shift onesKito Cheng1-0/+52
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang1-0/+97
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang1-50/+4
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng1-0/+12
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng1-0/+24
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng1-0/+32
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng1-0/+18
2021-06-08target/riscv: rvb: count bits setFrank Chang1-0/+13
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-0/+44
2021-06-08target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei1-39/+50
generated by cgit v1.1 at 2024-08-21 14:31:55 +0000