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AgeCommit message (Expand)AuthorFilesLines
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng1-0/+26
2021-06-08target/riscv: rvb: address calculationKito Cheng1-0/+24
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang1-0/+26
2021-06-08target/riscv: rvb: generalized reverseFrank Chang1-0/+31
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng1-0/+39
2021-06-08target/riscv: rvb: shift onesKito Cheng1-0/+52
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang1-0/+97
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang1-50/+4
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng1-0/+12
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng1-0/+24
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng1-0/+32
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng1-0/+18
2021-06-08target/riscv: rvb: count bits setFrank Chang1-0/+13
2021-06-08target/riscv: rvb: count leading/trailing zerosKito Cheng1-0/+44
2021-06-08target/riscv: Pass the same value to oprsz and maxsz.LIU Zhiwei1-39/+50
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis1-0/+6
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis7-35/+77
2021-01-18riscv: Add semihosting supportKeith Packard1-1/+36
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis1-14/+6
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis1-78/+45
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis1-1/+1
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis1-0/+340
2020-08-21target/riscv: check before allocating TCG tempsLIU Zhiwei2-8/+8
2020-08-21target/riscv: Clean up fmv.w.xLIU Zhiwei1-5/+1
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson1-16/+55
2020-08-21target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson1-0/+4
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson1-15/+1
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini8-0/+0
2020-07-22target/riscv: fix vector index load/store constraintsLIU Zhiwei1-1/+9
2020-07-22target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei1-0/+1
2020-07-13target/riscv: fix return value of do_opivx_widen()Frank Chang1-1/+1
2020-07-13target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang1-1/+1
2020-07-13target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang1-0/+5
2020-07-02target/riscv: vector compress instructionLIU Zhiwei1-0/+32
2020-07-02target/riscv: vector register gather instructionLIU Zhiwei1-0/+78
2020-07-02target/riscv: vector slide instructionsLIU Zhiwei1-0/+18
2020-07-02target/riscv: floating-point scalar move instructionsLIU Zhiwei1-0/+49
2020-07-02target/riscv: integer scalar move instructionLIU Zhiwei1-0/+60
2020-07-02target/riscv: integer extract instructionLIU Zhiwei1-0/+116
2020-07-02target/riscv: vector element index instructionLIU Zhiwei1-0/+25
2020-07-02target/riscv: vector iota instructionLIU Zhiwei1-0/+27
2020-07-02target/riscv: set-X-first mask bitLIU Zhiwei1-0/+28
2020-07-02target/riscv: vmfirst find-first-set mask bitLIU Zhiwei1-0/+32
2020-07-02target/riscv: vector mask population count vmpopcLIU Zhiwei1-0/+32
2020-07-02target/riscv: vector mask-register logical instructionsLIU Zhiwei1-0/+35
2020-07-02target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei1-0/+3
2020-07-02target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei1-0/+5
2020-07-02target/riscv: vector wideing integer reduction instructionsLIU Zhiwei1-0/+4
2020-07-02target/riscv: vector single-width integer reduction instructionsLIU Zhiwei1-0/+18
2020-07-02target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei1-0/+48
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