riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-09-01	target/riscv: Reorg csr instructions	Richard Henderson	1	-52/+122
2021-09-01	target/riscv: Use {get, dest}_gpr for integer load/store	Richard Henderson	1	-18/+20
2021-09-01	target/riscv: Use get_gpr in branches	Richard Henderson	1	-15/+10
2021-09-01	target/riscv: Use extracts for sraiw and srliw	Richard Henderson	1	-2/+12
2021-09-01	target/riscv: Use DisasExtend in shift operations	Richard Henderson	1	-70/+18
2021-09-01	target/riscv: Add DisasExtend to gen_arith*	Richard Henderson	1	-17/+22
2021-09-01	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	Richard Henderson	1	-22/+22
2021-06-08	target/riscv: add gen_shifti() and gen_shiftiw() helper functions	Frank Chang	1	-50/+4
2021-05-11	target/riscv: Consolidate RV32/64 16-bit instructions	Alistair Francis	1	-0/+6
2021-05-11	target/riscv: Consolidate RV32/64 32-bit instructions	Alistair Francis	1	-4/+12
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini	1	-0/+577