Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-05-11 | target/riscv: Consolidate RV32/64 32-bit instructions | Alistair Francis | 1 | -88/+0 |
2020-08-25 | target/riscv: Allow generating hlv/hlvx/hsv instructions | Alistair Francis | 1 | -0/+5 |
2020-07-02 | target/riscv: add vector amo operations | LIU Zhiwei | 1 | -0/+11 |
2019-03-13 | target/riscv: Convert RV64D insns to decodetree | Bastian Koppelmann | 1 | -0/+8 |
2019-03-13 | target/riscv: Convert RV64F insns to decodetree | Bastian Koppelmann | 1 | -0/+6 |
2019-03-13 | target/riscv: Convert RV64A insns to decodetree | Bastian Koppelmann | 1 | -0/+13 |
2019-03-13 | target/riscv: Convert RVXM insns to decodetree | Bastian Koppelmann | 1 | -0/+7 |
2019-03-13 | target/riscv: Convert RVXI arithmetic insns to decodetree | Bastian Koppelmann | 1 | -0/+13 |
2019-03-13 | target/riscv: Convert RV64I load/store insns to decodetree | Bastian Koppelmann | 1 | -0/+25 |