riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-04-26	exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header	Philippe Mathieu-Daudé	1	-0/+2
2023-09-11	target/riscv: Allocate itrigger timers only once	Akihiko Odaki	1	-1/+2
2023-01-06	target/riscv: Add itrigger support when icount is enabled	LIU Zhiwei	1	-0/+1
2023-01-06	target/riscv: Add itrigger support when icount is not enabled	LIU Zhiwei	1	-0/+12
2022-09-27	target/riscv: debug: Add initial support of type 6 trigger	Frank Chang	1	-0/+18
2022-09-27	target/riscv: debug: Create common trigger actions function	Frank Chang	1	-0/+13
2022-09-27	target/riscv: debug: Introduce tinfo CSR	Frank Chang	1	-0/+2
2022-09-27	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	Frank Chang	1	-7/+0
2022-09-27	target/riscv: debug: Introduce build_tdata1() to build tdata1 register content	Frank Chang	1	-0/+2
2022-09-27	target/riscv: debug: Determine the trigger type from tdata1.type	Frank Chang	1	-9/+4
2022-04-22	target/riscv: csr: Hook debug CSR read/write	Bin Meng	1	-0/+2
2022-04-22	target/riscv: debug: Implement debug related TCGCPUOps	Bin Meng	1	-0/+4
2022-04-22	target/riscv: Add initial support for the Sdtrig extension	Bin Meng	1	-0/+108