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cpu_helper.c
Age
Commit message (
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Author
Files
Lines
2020-08-25
target/riscv: Update the Hypervisor trap return/entry
Alistair Francis
1
-10
/
+6
2020-08-25
target/riscv: Fix the interrupt cause code
Alistair Francis
1
-2
/
+3
2020-08-25
target/riscv: Convert MSTATUS MTL to GVA
Alistair Francis
1
-4
/
+20
2020-08-25
target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
Alistair Francis
1
-35
/
+25
2020-08-25
target/riscv: Allow setting a two-stage lookup in the virt status
Alistair Francis
1
-0
/
+18
2020-08-21
target/riscv: Change the TLB page size depends on PMP entries.
Zong Li
1
-2
/
+8
2020-08-21
target/riscv: Fix the translation of physical address
Zong Li
1
-2
/
+3
2020-06-19
target/riscv: Report errors validating 2nd-stage PTEs
Alistair Francis
1
-2
/
+7
2020-06-19
target/riscv: Set access as data_load when validating stage-2 PTEs
Alistair Francis
1
-1
/
+1
2020-06-03
target/riscv: Drop support for ISA spec version 1.09.1
Alistair Francis
1
-53
/
+29
2020-04-29
riscv: Fix Stage2 SV32 page table walk
Anup Patel
1
-6
/
+1
2020-04-29
riscv: AND stage-1 and stage-2 protection flags
Alistair Francis
1
-3
/
+5
2020-04-29
riscv: Don't use stage-2 PTE lookup protection flags
Alistair Francis
1
-1
/
+2
2020-03-16
target/riscv: Fix VS mode interrupts forwarding.
Rajnesh Kanwal
1
-1
/
+8
2020-02-27
target/riscv: Emulate TIME CSRs for privileged mode
Anup Patel
1
-0
/
+5
2020-02-27
target/riscv: Add the MSTATUS_MPV_ISSET helper macro
Alistair Francis
1
-2
/
+2
2020-02-27
target/riscv: Add support for the 32-bit MSTATUSH CSR
Alistair Francis
1
-0
/
+17
2020-02-27
target/riscv: Set htval and mtval2 on execptions
Alistair Francis
1
-0
/
+10
2020-02-27
target/riscv: Raise the new execptions when 2nd stage translation fails
Alistair Francis
1
-6
/
+18
2020-02-27
target/riscv: Implement second stage MMU
Alistair Francis
1
-19
/
+174
2020-02-27
target/riscv: Allow specifying MMU stage
Alistair Francis
1
-9
/
+28
2020-02-27
target/riscv: Disable guest FP support based on virtual status
Alistair Francis
1
-0
/
+3
2020-02-27
target/riscv: Add hypvervisor trap support
Alistair Francis
1
-10
/
+59
2020-02-27
target/ricsv: Flush the TLB on virtulisation mode changes
Alistair Francis
1
-0
/
+5
2020-02-27
target/riscv: Add support for virtual interrupt setting
Alistair Francis
1
-5
/
+28
2020-02-27
target/riscv: Add virtual register swapping function
Alistair Francis
1
-0
/
+61
2020-02-27
target/riscv: Add the force HS exception mode
Alistair Francis
1
-0
/
+18
2020-02-27
target/riscv: Add the virtulisation mode
Alistair Francis
1
-0
/
+18
2020-02-27
target/riscv: Add support for the new execption numbers
Alistair Francis
1
-2
/
+5
2020-01-15
tcg: Search includes from the project root source directory
Philippe Mathieu-Daudé
1
-1
/
+1
2019-11-14
target/riscv: Remove atomic accesses to MIP CSR
Alistair Francis
1
-30
/
+18
2019-10-28
linux-user/riscv: Propagate fault address
Giuseppe Musacchio
1
-1
/
+4
2019-10-28
RISC-V: Implement cpu_do_transaction_failed
Palmer Dabbelt
1
-4
/
+7
2019-10-28
RISC-V: Handle bus errors in the page table walker
Palmer Dabbelt
1
-3
/
+9
2019-09-17
riscv: rv32: Root page table address can be larger than 32-bit
Bin Meng
1
-5
/
+5
2019-09-17
target/riscv: Create function to test if FP is enabled
Alistair Francis
1
-0
/
+10
2019-06-25
RISC-V: Clear load reservations on context switch and SC
Joel Sing
1
-0
/
+10
2019-06-23
RISC-V: Fix a PMP check with the correct access size
Hesham Almatary
1
-2
/
+1
2019-06-23
RISC-V: Check PMP during Page Table Walks
Hesham Almatary
1
-1
/
+9
2019-06-23
RISC-V: Check for the effective memory privilege mode during PMP checks
Hesham Almatary
1
-1
/
+9
2019-06-23
RISC-V: Raise access fault exceptions on PMP violations
Hesham Almatary
1
-3
/
+6
2019-06-23
RISC-V: Only Check PMP if MMU translation succeeds
Hesham Almatary
1
-0
/
+1
2019-06-23
target/riscv: Implement riscv_cpu_unassigned_access
Michael Clark
1
-0
/
+16
2019-06-10
target/riscv: Use env_cpu, env_archcpu
Richard Henderson
1
-6
/
+4
2019-05-24
target/riscv: Improve the scause logic
Alistair Francis
1
-1
/
+1
2019-05-24
target/riscv: Trigger interrupt on MIP update asynchronously
Alistair Francis
1
-6
/
+27
2019-05-10
tcg: Use CPUClass::tlb_fill in cputlb.c
Richard Henderson
1
-6
/
+0
2019-05-10
target/riscv: Convert to CPUClass::tlb_fill
Richard Henderson
1
-25
/
+21
2019-03-19
RISC-V: Update load reservation comment in do_interrupt
Michael Clark
1
-1
/
+7
2019-03-19
RISC-V: Convert trap debugging to trace events
Michael Clark
1
-9
/
+3
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