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| author | Anup Patel <anup.patel@wdc.com> | 2020-02-02 19:12:16 +0530 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-02-27 13:46:36 -0800 |
| commit | c695724868ce4049fd79c5a509880dbdf171e744 (patch) | |
| tree | e399f75e9a1aeb4f9c64dfa9a5e985413d5e8d24 /target/riscv/cpu_helper.c | |
| parent | acead54c78c7294612f529413673eb4286fb8b18 (diff) | |
| download | qemu-c695724868ce4049fd79c5a509880dbdf171e744.zip qemu-c695724868ce4049fd79c5a509880dbdf171e744.tar.gz qemu-c695724868ce4049fd79c5a509880dbdf171e744.tar.bz2 | |
target/riscv: Emulate TIME CSRs for privileged mode
Currently, TIME CSRs are emulated only for user-only mode. This
patch add TIME CSRs emulation for privileged mode.
For privileged mode, the TIME CSRs will return value provided
by rdtime callback which is registered by QEMU machine/platform
emulation (i.e. CLINT emulation). If rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.
We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'target/riscv/cpu_helper.c')
| -rw-r--r-- | target/riscv/cpu_helper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 29a1b37..5ea5d13 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -258,6 +258,11 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value) return old; } +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)) +{ + env->rdtime_fn = fn; +} + void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) { if (newpriv > PRV_M) { |