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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza1-4/+0
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza1-4/+0
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza1-7/+3
2023-03-01target/riscv/cpu.c: error out if EPMP is enabled without PMPDaniel Henrique Barboza1-2/+7
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza1-5/+1
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza1-0/+6
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang1-1/+1
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner1-0/+31
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner1-1/+1
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner1-0/+2
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner1-0/+2
2023-01-20target/riscv: Use TARGET_FMT_lx for env->mhartidBin Meng1-3/+3
2023-01-20target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()Daniel Henrique Barboza1-194/+205
2023-01-20target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza1-0/+40
2023-01-20target/riscv/cpu.c: Fix elen checkDongxue Zhang1-1/+1
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner1-0/+7
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng1-0/+4
2022-12-16target/riscv: Convert to 3-phase resetPeter Maydell1-4/+8
2022-10-26target/riscv: Convert to tcg_ops restore_state_to_opcRichard Henderson1-2/+7
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson1-2/+2
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson1-0/+13
2022-09-27target/riscv: Set the CPU resetvec directlyAlistair Francis1-10/+3
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra1-0/+12
2022-09-07target/riscv: Add stimecmp supportAtish Patra1-0/+9
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-5/+4
2022-09-07target/riscv: Add xicondops in ISA entryRahul Pathak1-0/+1
2022-09-07target/riscv: Add Zihintpause supportDao Lu1-0/+2
2022-09-07target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...eopXD1-0/+1
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li1-0/+5
2022-09-07target/riscv: H extension depends on I extensionWeiwei Li1-0/+6
2022-09-07target/riscv: Add check for supported privilege mode combinationsWeiwei Li1-0/+6
2022-09-07target/riscv: move zmmul out of the experimental propertiesWeiwei Li1-1/+2
2022-09-07target/riscv: Force disable extensions if priv spec version does not matchAnup Patel1-56/+94
2022-07-27RISC-V: Allow both Zmmul and MPalmer Dabbelt1-5/+0
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel1-4/+8
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis1-1/+1
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra1-2/+1
2022-07-03target/riscv: pmu: Rename the counters extension to pmuAtish Patra1-2/+2
2022-06-10target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis1-11/+46
2022-06-10target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD1-0/+2
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker1-1/+1
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