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path: root/target/riscv/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2023-07-19target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcfDaniel Henrique Barboza1-1/+2
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner1-0/+8
2023-07-10target/riscv/cpu.c: create KVM mock propertiesDaniel Henrique Barboza1-0/+36
2023-07-10target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()Daniel Henrique Barboza1-2/+1
2023-07-10target/riscv/cpu.c: add satp_mode properties earlierDaniel Henrique Barboza1-4/+2
2023-07-10target/riscv/kvm.c: add multi-letter extension KVM propertiesDaniel Henrique Barboza1-0/+8
2023-07-10target/riscv: add KVM specific MISA propertiesDaniel Henrique Barboza1-0/+5
2023-07-10target/riscv/cpu: add misa_ext_info_arr[]Daniel Henrique Barboza1-28/+82
2023-07-10target/riscv: use KVM scratch CPUs to init KVM propertiesDaniel Henrique Barboza1-0/+6
2023-07-10target/riscv/cpu.c: restrict 'marchid' valueDaniel Henrique Barboza1-7/+53
2023-07-10target/riscv/cpu.c: restrict 'mimpid' valueDaniel Henrique Barboza1-2/+32
2023-07-10target/riscv/cpu.c: restrict 'mvendorid' valueDaniel Henrique Barboza1-1/+37
2023-07-10target/riscv: skip features setup for KVM CPUsDaniel Henrique Barboza1-10/+25
2023-07-10target/riscv: Expose properties for BF16 extensionsWeiwei Li1-0/+7
2023-07-10target/riscv: Add properties for BF16 extensionsWeiwei Li1-0/+20
2023-07-10target/riscv: Add RVV registers to logIvan Klokov1-1/+56
2023-07-10target/riscv/cpu.c: fix veyron-v1 CPU propertiesDaniel Henrique Barboza1-0/+3
2023-07-10target/riscv: Use xl instead of mxl for disassembleLIU Zhiwei1-1/+2
2023-06-28target/riscv: Restrict KVM-specific fields from ArchCPUPhilippe Mathieu-Daudé1-1/+1
2023-06-13target/riscv: Enable PC-relative translationWeiwei Li1-10/+21
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li1-0/+1
2023-06-13target/riscv: smstateen knobsMayuresh Chitale1-1/+2
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza1-2/+2
2023-06-13target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()Daniel Henrique Barboza1-12/+47
2023-06-13target/riscv/cpu.c: validate extensions before riscv_timer_init()Daniel Henrique Barboza1-7/+4
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()Daniel Henrique Barboza1-17/+33
2023-06-13target/riscv/cpu.c: add priv_spec validate/disable_exts helpersDaniel Henrique Barboza1-35/+56
2023-06-13target/riscv: Mask the implicitly enabled extensions in isa_string based on p...Weiwei Li1-1/+2
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza1-4/+4
2023-06-13target/riscv/cpu.c: remove set_priv_version()Daniel Henrique Barboza1-17/+12
2023-06-13target/riscv/cpu.c: remove set_vext_version()Daniel Henrique Barboza1-6/+1
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_v()Daniel Henrique Barboza1-41/+48
2023-06-13target/riscv: Move zc* out of the experimental propertiesWeiwei Li1-8/+8
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak1-0/+38
2023-05-05target/riscv: add TYPE_RISCV_DYNAMIC_CPUDaniel Henrique Barboza1-4/+16
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei1-1/+1
2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li1-2/+3
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza1-31/+10
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza1-9/+8
2023-05-05target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()Daniel Henrique Barboza1-2/+1
2023-05-05target/riscv: remove riscv_cpu_sync_misa_cfg()Daniel Henrique Barboza1-52/+0
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza1-7/+5
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza1-3/+3
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza1-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza1-5/+4
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza1-6/+5
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza1-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza1-5/+5
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza1-8/+7
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza1-13/+13
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