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cpu.c
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Author
Files
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2023-07-19
target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf
Daniel Henrique Barboza
1
-1
/
+2
2023-07-10
riscv: Add support for the Zfa extension
Christoph Müllner
1
-0
/
+8
2023-07-10
target/riscv/cpu.c: create KVM mock properties
Daniel Henrique Barboza
1
-0
/
+36
2023-07-10
target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()
Daniel Henrique Barboza
1
-2
/
+1
2023-07-10
target/riscv/cpu.c: add satp_mode properties earlier
Daniel Henrique Barboza
1
-4
/
+2
2023-07-10
target/riscv/kvm.c: add multi-letter extension KVM properties
Daniel Henrique Barboza
1
-0
/
+8
2023-07-10
target/riscv: add KVM specific MISA properties
Daniel Henrique Barboza
1
-0
/
+5
2023-07-10
target/riscv/cpu: add misa_ext_info_arr[]
Daniel Henrique Barboza
1
-28
/
+82
2023-07-10
target/riscv: use KVM scratch CPUs to init KVM properties
Daniel Henrique Barboza
1
-0
/
+6
2023-07-10
target/riscv/cpu.c: restrict 'marchid' value
Daniel Henrique Barboza
1
-7
/
+53
2023-07-10
target/riscv/cpu.c: restrict 'mimpid' value
Daniel Henrique Barboza
1
-2
/
+32
2023-07-10
target/riscv/cpu.c: restrict 'mvendorid' value
Daniel Henrique Barboza
1
-1
/
+37
2023-07-10
target/riscv: skip features setup for KVM CPUs
Daniel Henrique Barboza
1
-10
/
+25
2023-07-10
target/riscv: Expose properties for BF16 extensions
Weiwei Li
1
-0
/
+7
2023-07-10
target/riscv: Add properties for BF16 extensions
Weiwei Li
1
-0
/
+20
2023-07-10
target/riscv: Add RVV registers to log
Ivan Klokov
1
-1
/
+56
2023-07-10
target/riscv/cpu.c: fix veyron-v1 CPU properties
Daniel Henrique Barboza
1
-0
/
+3
2023-07-10
target/riscv: Use xl instead of mxl for disassemble
LIU Zhiwei
1
-1
/
+2
2023-06-28
target/riscv: Restrict KVM-specific fields from ArchCPU
Philippe Mathieu-Daudé
1
-1
/
+1
2023-06-13
target/riscv: Enable PC-relative translation
Weiwei Li
1
-10
/
+21
2023-06-13
target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
Weiwei Li
1
-0
/
+1
2023-06-13
target/riscv: smstateen knobs
Mayuresh Chitale
1
-1
/
+2
2023-06-13
target/riscv: rework write_misa()
Daniel Henrique Barboza
1
-2
/
+2
2023-06-13
target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
Daniel Henrique Barboza
1
-12
/
+47
2023-06-13
target/riscv/cpu.c: validate extensions before riscv_timer_init()
Daniel Henrique Barboza
1
-7
/
+4
2023-06-13
target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
Daniel Henrique Barboza
1
-17
/
+33
2023-06-13
target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
Daniel Henrique Barboza
1
-35
/
+56
2023-06-13
target/riscv: Mask the implicitly enabled extensions in isa_string based on p...
Weiwei Li
1
-1
/
+2
2023-06-13
target/riscv: add PRIV_VERSION_LATEST
Daniel Henrique Barboza
1
-4
/
+4
2023-06-13
target/riscv/cpu.c: remove set_priv_version()
Daniel Henrique Barboza
1
-17
/
+12
2023-06-13
target/riscv/cpu.c: remove set_vext_version()
Daniel Henrique Barboza
1
-6
/
+1
2023-06-13
target/riscv/cpu.c: add riscv_cpu_validate_v()
Daniel Henrique Barboza
1
-41
/
+48
2023-06-13
target/riscv: Move zc* out of the experimental properties
Weiwei Li
1
-8
/
+8
2023-05-05
target/riscv: add Ventana's Veyron V1 CPU
Rahul Pathak
1
-0
/
+38
2023-05-05
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
Daniel Henrique Barboza
1
-4
/
+16
2023-05-05
target/riscv: Add a general status enum for extensions
LIU Zhiwei
1
-1
/
+1
2023-05-05
target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx
Weiwei Li
1
-2
/
+3
2023-05-05
target/riscv/cpu.c: redesign register_cpu_props()
Daniel Henrique Barboza
1
-31
/
+10
2023-05-05
target/riscv: add RVG and remove cpu->cfg.ext_g
Daniel Henrique Barboza
1
-9
/
+8
2023-05-05
target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
Daniel Henrique Barboza
1
-2
/
+1
2023-05-05
target/riscv: remove riscv_cpu_sync_misa_cfg()
Daniel Henrique Barboza
1
-52
/
+0
2023-05-05
target/riscv: remove cpu->cfg.ext_v
Daniel Henrique Barboza
1
-7
/
+5
2023-05-05
target/riscv: remove cpu->cfg.ext_j
Daniel Henrique Barboza
1
-3
/
+3
2023-05-05
target/riscv: remove cpu->cfg.ext_h
Daniel Henrique Barboza
1
-5
/
+5
2023-05-05
target/riscv: remove cpu->cfg.ext_u
Daniel Henrique Barboza
1
-5
/
+4
2023-05-05
target/riscv: remove cpu->cfg.ext_s
Daniel Henrique Barboza
1
-6
/
+5
2023-05-05
target/riscv: remove cpu->cfg.ext_m
Daniel Henrique Barboza
1
-5
/
+5
2023-05-05
target/riscv: remove cpu->cfg.ext_e
Daniel Henrique Barboza
1
-5
/
+5
2023-05-05
target/riscv: remove cpu->cfg.ext_i
Daniel Henrique Barboza
1
-8
/
+7
2023-05-05
target/riscv: remove cpu->cfg.ext_f
Daniel Henrique Barboza
1
-13
/
+13
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