riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-09-17	target/riscv: Use both register name and ABI name	Atish Patra	1	-8/+11
2019-08-19	target/riscv: rationalise softfloat includes	Alex Bennée	1	-0/+1
2019-06-25	RISC-V: Clear load reservations on context switch and SC	Joel Sing	1	-0/+1
2019-06-25	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt	1	-0/+1
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt	1	-0/+1
2019-06-25	target/riscv: Add support for disabling/enabling Counters	Alistair Francis	1	-0/+1
2019-06-25	target/riscv: Remove user version information	Alistair Francis	1	-23/+9
2019-06-25	target/riscv: Require either I or E base extension	Alistair Francis	1	-0/+6
2019-06-25	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis	1	-3/+5
2019-06-24	target/riscv: Restructure deprecatd CPUs	Alistair Francis	1	-8/+10
2019-06-23	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark	1	-0/+1
2019-06-23	target/riscv: Allow setting ISA extensions via CPU props	Alistair Francis	1	-2/+68
2019-06-11	qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h	Markus Armbruster	1	-0/+1
2019-06-10	cpu: Introduce cpu_set_cpustate_pointers	Richard Henderson	1	-2/+1
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	1	-0/+14
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis	1	-0/+49
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson	1	-8/+8
2019-05-10	target/riscv: Convert to CPUClass::tlb_fill	Richard Henderson	1	-3/+2
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	1	-19/+18
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	1	-13/+4
2019-03-19	target/riscv: Remove unused struct	Alistair Francis	1	-6/+0
2019-03-19	RISC-V: Add hooks to use the gdb xml files.	Jim Wilson	1	-1/+8
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark	1	-1/+1
2019-01-09	RISC-V: Implement existential predicates for CSRs	Michael Clark	1	-0/+6
2018-12-20	riscv/cpu: use device_class_set_parent_realize	Mao Zhongyi	1	-2/+2
2018-10-17	RISC-V: Update CSR and interrupt definitions	Michael Clark	1	-2/+4
2018-05-18	target/riscv: Honor CPU_DUMP_FPU	Richard Henderson	1	-5/+7
2018-05-06	RISC-V: Update E and I extension order	Michael Clark	1	-1/+1
2018-03-28	RISC-V: Convert cpu definition to future model	Michael Clark	1	-54/+69
2018-03-20	RISC-V: Fix riscv_isa_string memory size bug	Michael Clark	1	-6/+6
2018-03-07	RISC-V CPU Core Definition	Michael Clark	1	-0/+432