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2022-01-04target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()Daniel Henrique Barboza1-1/+6
MMCR0 writes will change only MMCR0 bits which are used to calculate HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine register will be changed during this operation. This means that hreg_compute_hflags() is overkill for what we need to do. pmu_update_summaries() is already updating HFLAGS_INSN_CNT without calling hreg_compure_hflags(). Let's do the same for the other 2 MMCR0 hflags. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220103224746.167831-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Use env->pnc_cyc_cntRichard Henderson1-98/+9
Use the cached pmc_cyc_cnt value in pmu_update_cycles and pmc_update_overflow_timer. This leaves pmc_get_event and pmc_is_inactive unused, so remove them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103224746.167831-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Rewrite pmu_increment_insnsRichard Henderson1-29/+49
Use the cached pmc_ins_cnt value. Unroll the loop over the different PMC counters. Treat the PMC4 run-latch specially. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103224746.167831-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Cache per-pmc insn and cycle count settingsRichard Henderson6-20/+58
This is the combination of frozen bit and counter type, on a per counter basis. So far this is only used by HFLAGS_INSN_CNT, but will be used more later. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [danielhb: fixed PMC4 cyc_cnt shift, insn run latch code, MMCR0_FC handling, "PMC[1-6]" comment] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220103224746.167831-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Stop passing excp_model aroundFabiano Rosas1-22/+21
We can just access it directly in powerpc_excp. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ clg: Took into account removal of inline ] Message-Id: <20211229165751.3774248-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Move system call vectored code togetherFabiano Rosas1-8/+5
Now that 'vector' is known before calling the interrupt-specific setup code, we can move all of the scv setup into one place. No functional change intended. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211229165751.3774248-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Set vector earlierFabiano Rosas1-8/+8
None of the interrupt setup code touches 'vector', so we can move it earlier in the function. This will allow us to later move the System Call Vectored setup that is on the top level into the POWERPC_EXCP_SYSCALL_VECTORED code block. This patch also moves the verification for when 'excp' does not have an address associated with it. We now bail a little earlier when that is the case. This should not cause any visible effects. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20211229165751.3774248-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Add excp_vectors bounds checkFabiano Rosas1-3/+4
The next patch will start accessing the excp_vectors array earlier in the function, so add a bounds check as first thing here. This converts the empty return on POWERPC_EXCP_NONE to an error. This exception number never reaches this function and if it does it probably means something else went wrong up the line. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20211229165751.3774248-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: powerpc_excp: Set alternate SRRs directlyFabiano Rosas1-15/+8
There are currently only two interrupts that use alternate SRRs, so let them write to them directly during the setup code. No functional change intended. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20211229165751.3774248-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: do not silence snan in xscvspdpnMatheus Ferst1-4/+1
The non-signalling versions of VSX scalar convert to shorter/longer precision insns doesn't silence SNaNs in the hardware. To better match this behavior, use the non-arithmatic conversion of helper_todouble instead of float32_to_float64. A test is added to prevent future regressions. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211228120310.1957990-1-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Dump specific registersCédric Le Goater1-6/+21
Rework slightly ppc_cpu_dump_state() to replace the various 'if' statements with a 'switch'. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-9-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-10-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Introduce a store helper for SPR_40x_PIDCédric Le Goater3-1/+10
The PID SPR of the 405 CPU contains the translation ID of the TLB which is a 8-bit field. Enforce the mask with a store helper. Cc: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-8-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-9-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Restore TCR and STR write handlersCédric Le Goater6-2/+30
The 405 timers were broken when booke support was added. Assumption was made that the register numbers were the same but it's not : SPR_BOOKE_TSR (0x150) SPR_BOOKE_TCR (0x154) SPR_40x_TSR (0x3D8) SPR_40x_TCR (0x3DA) Cc: Christophe Leroy <christophe.leroy@c-s.fr> Fixes: ddd1055b07fd ("PPC: booke timers") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04ppc/ppc405: Activate MMU logsCédric Le Goater2-139/+122
There is no need to deactivate MMU logging at compile time. Remove all use of defines. Only keep DUMP_PAGE_TABLES for another series since page tables could be dumped from the monitor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211222064025.1541490-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103063441.3424853-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Print out literal exception names in logsCédric Le Goater1-1/+74
It facilitates reading the logs when mask CPU_LOG_INT is activated. We should do the same for error codes. Cc: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211222064025.1541490-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220103063441.3424853-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Remove static inlineCédric Le Goater1-6/+6
The compiler should know better how to inline code if necessary. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103063441.3424853-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Check effective address validityCédric Le Goater2-0/+6
For Radix translation, the EA range is 64-bits. when EA(2:11) are nonzero, a segment interrupt should occur. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20211231073122.3183583-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-04target/ppc: Improve logging in Radix MMUCédric Le Goater1-3/+52
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211222071002.1568894-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17PPC64/TCG: Implement 'rfebb' instructionDaniel Henrique Barboza6-0/+85
An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The following operations happens during an EBB: - Global Enable (GE) bit of BESCR is set to 0; - bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set to the the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but the next patches will use the remaining bits. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-9-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) eventDaniel Henrique Barboza5-4/+42
PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. To make this work properly we also need to force a new translation block each time SPR_CTRL is written. A small tweak in pmu_increment_insns() is then needed to only increment this event if the thread has the run latch. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: enable PMU instruction countDaniel Henrique Barboza7-1/+146
The PMU is already counting cycles by calculating time elapsed in nanoseconds. Counting instructions is a different matter and requires another approach. This patch adds the capability of counting completed instructions (Perf event PM_INST_CMPL) by counting the amount of instructions translated in each translation block right before exiting it. A new pmu_count_insns() helper in translation.c was added to do that. After verifying that the PMU is counting instructions, call helper_insns_inc(). This new helper from power8-pmu.c will add the instructions to the relevant counters. It'll also be responsible for triggering counter negative overflows as it is already being done with cycles. To verify whether the PMU is counting instructions or now, a new hflags named 'HFLAGS_INSN_CNT' is introduced. This flag will match the internal state of the PMU. We're be using this flag to avoid calling helper_insn_inc() when we do not have a valid instruction event being sampled. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-7-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: enable PMU counter overflow with cycle eventsDaniel Henrique Barboza2-0/+73
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative conditions are enabled. This means that if the counter value overflows (i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert can trigger an event-based exception (to be implemented in the next patches) if the MMCR0_EBE bit is set. For now, overflowing the counter when the PMC is counting cycles will just trigger a performance monitor alert. This is done by starting the overflow timer to expire in the moment the overflow would be occuring. The timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will trigger the PMU alert and, if the conditions are met, an EBB exception. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: PMU: update counters on MMCR1 writeDaniel Henrique Barboza5-1/+21
MMCR1 determines the events to be sampled by the PMU. Updating the counters at every MMCR1 write ensures that we're not sampling more or less events by looking only at MMCR0 and the PMCs. It is worth noticing that both the Book3S PowerPC PMU, and this IBM Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to control the PMU. These three registers aren't being handled in this initial implementation, so for now we're controlling all the PMU aspects using MMCR0, MMCR1 and the PMCs. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: PMU: update counters on PMCs r/wDaniel Henrique Barboza5-8/+51
Calling pmu_update_cycles() on every PMC read/write operation ensures that the values being fetched are up to date with the current PMU state. In theory we can get away by just trapping PMCs reads, but we're going to trap PMC writes to deal with counter overflow logic later on. Let's put the required wiring for that and make our lives a bit easier in the next patches. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: PMU basic cycle count for pseries TCGDaniel Henrique Barboza6-4/+157
This patch adds the barebones of the PMU logic by enabling cycle counting. The overall logic goes as follows: - MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid having to spin the PMU right at system init; - to retrieve the events that are being profiled, pmc_get_event() will check the current MMCR0 and MMCR1 value and return the appropriate PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation dependent value of PMU_EVENT_CYCLES. These events are supported by IBM Power chips since Power8, at least, and the Linux Perf driver makes use of these events until kernel v5.15. For PMC1, event 0xF0 is the architected PowerISA event for cycles. Event 0xFE is the architected PowerISA event for instructions; - if the counter is frozen, either via the global MMCR0_FC bit or its individual frozen counter bits, PMU_EVENT_INACTIVE is returned; - pmu_update_cycles() will go through each counter and update the values of all PMCs that are counting cycles. This function will be called every time a MMCR0 update is done to keep counters values up to date. Upcoming patches will use this function to allow the counters to be properly updated during read/write of the PMCs and MMCR1 writes. Given that the base CPU frequency is fixed at 1Ghz for both powernv and pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU cycle. Cycle value is then calculated by adding the elapsed time, in nanoseconds, of the last cycle update done via pmu_update_cycles(). Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: introduce PMUEventType and PMU overflow timersDaniel Henrique Barboza5-0/+127
This patch starts an IBM Power8+ compatible PMU implementation by adding the representation of PMU events that we are going to sample, PMUEventType. This enum represents a Perf event that is being sampled by a specific counter 'sprn'. Events that aren't available (i.e. no event was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are inactive due to frozen counter bits state are of type 'PMU_EVENT_INACTIVE'. Other types added in this patch are PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added later on. Let's also add the required PMU cycle overflow timers. They will be used to trigger cycle overflows when cycle events are being sampled. This timer will call cpu_ppc_pmu_timer_cb(), which in turn calls fire_PMC_interrupt(). Both functions are stubs that will be implemented later on when EBB support is added. Two new helper files are created to host this new logic. cpu_ppc_pmu_init() will init all overflow timers during CPU init time. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211201151734.654994-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"Fabiano Rosas1-9/+12
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2. It breaks the --disable-tcg build: ../target/ppc/excp_helper.c:463:29: error: implicit declaration of function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration] We should not have TCG code in powerpc_excp because some kvm-only routines use it indirectly to dispatch interrupts. See kvm_handle_debug, spapr_mce_req_event and spapr_do_system_reset_on_cpu. We can re-introduce the change once we have split the interrupt injection code between KVM and TCG. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Fix e6500 bootFabiano Rosas2-1/+17
When Altivec support was added to the e6500 kernel in 2012[1], the QEMU code was not changed, so we don't register the VPU/VPUA exceptions for the e6500: qemu: fatal: Raised an exception without defined vector 73 Note that the error message says 73, instead of 32, which is the IVOR for VPU. This is because QEMU knows only knows about the VPU interrupt for the 7400s. In theory, we should not be raising _that_ VPU interrupt, but instead another one specific for the e6500. We unfortunately cannot register e6500-specific VPU/VPUA interrupts because the SPEU/EFPDI interrupts also use IVOR32/33. These are present only in the e500v1/2 versions. From the user manual: e500v1, e500v2: only SPEU/EFPDI/EFPRI e500mc, e5500: no SPEU/EFPDI/EFPRI/VPU/VPUA e6500: only VPU/VPUA So I'm leaving IVOR32/33 as SPEU/EFPDI, but altering the dispatch code to convert the VPU #73 to a #32 when we're in the e6500. Since the handling for SPEU and VPU is the same this is the only change that's needed. The EFPDI is not implemented and will cause an abort. I don't think it worth it changing the error message to take VPUA into consideration, so I'm not changing anything there. This bug was discussed in the thread: https://lists.gnu.org/archive/html/qemu-ppc/2021-06/msg00222.html 1- https://git.kernel.org/torvalds/c/cd66cc2ee52 Reported-by: <mario@locati.it> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211213133542.2608540-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: move xscvqpdp to decodetreeMatheus Ferst5-20/+21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: fix xscvqpdp register accessMatheus Ferst1-2/+3
This instruction has VRT and VRB fields instead of T/TX and B/BX. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Move xs{max,min}[cj]dp to decodetreeVictor Colombo3-11/+40
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20211213120958.24443-3-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Fix xs{max, min}[cj]dp to use VSX registersVictor Colombo3-10/+10
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using vector registers when they should be using VSX ones. This happens because the instructions are using GEN_VSX_HELPER_R3, which adds 32 to the register numbers, effectively making them vector registers. This patch fixes it by changing these instructions to use GEN_VSX_HELPER_X3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: remove 401/403 CPUsCédric Le Goater7-608/+4
They have been there since 2007 without any board using them, most were protected by a TODO define. Drop support. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211202191108.1291515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Set 601v exception model idFabiano Rosas1-0/+1
The exception model id for 601v has been removed without mention why. I assume it was inadvertent and restore it here. Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling") Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211208123029.2052625-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Remove 603e exception modelFabiano Rosas3-33/+2
The 603e uses the same exception code as 603 so we don't need a dedicated entry for it. This is only a removal of redundant code, no functional change. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211208123029.2052625-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Fix MPCxxx FPU interrupt addressFabiano Rosas1-2/+2
The Floating-point Unavailable and Decrementer interrupts are being registered at the same 0x900 address. The FPU should be at 0x800 instead. Verified on MPC555, MPC860 and MPC885 user manuals. Reported-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211208123029.2052625-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Remove the software TLB model of 7450 CPUsFabiano Rosas8-137/+6
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448) The QEMU-side software TLB implementation for the 7450 family of CPUs is being removed due to lack of known users in the real world. The last users in the code were removed by the two previous commits. A brief history: The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU models in switches...") with the mention that Linux was not able to handle the TLB miss interrupts and the MMU model would be kept disabled. At some point later, commit 8ca3f6c382 ("Allow selection of all defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450 family without further justification. We have since the year 2011 [1] been unable to run OpenBIOS in the 7450s and have not heard of any other software that is used with those CPUs in QEMU. Attempts were made to find a guest OS that implemented the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS 3.15. All CPUs that registered this feature were moved to an MMU model that replaces the software TLB with a QEMU hardware TLB implementation. They can now run the same software as the 7400 CPUs, including the OSes mentioned above. References: - https://bugs.launchpad.net/qemu/+bug/812398 https://gitlab.com/qemu-project/qemu/-/issues/86 - https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html message id: 20211119134431.406753-1-farosas@linux.ibm.com Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Disable unused facilities in the e600 CPUFabiano Rosas1-5/+1
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs, it has an optional software TLB feature. We have determined that there is no OS software support for the 7450 software TLB available these days. See the previous commit for more information. This patch disables the SPRs and instructions related to software TLB from the e600 CPU. No functional change intended. These facilities should be used by the OS in interrupt handlers for interrupts that QEMU never generates. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Disable software TLB for the 7450 familyFabiano Rosas1-15/+10
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)* We have since 2011 [1] been unable to run OpenBIOS in the 7450s and have not heard of any other software that is used with those CPUs in QEMU. A current discussion [2] shows that the 7450 software TLB is unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS 3.15. With no known support in firmware or OS, this means that no code for any of the 7450 CPUs is ever ran in QEMU. Since the implementation in QEMU of the 7400 MMU is the same as the 7450, except for the software TLB vs. hardware TLB search, this patch changes all 7450 cpus to the 7400 MMU model. This has the practical effect of disabling the software TLB feature while keeping other aspects of address translation working as expected. This allow us to run software on the 7450 family again. *- note that the 7448 is currently aliased in QEMU for a 7400, so it is unaffected by this change. 1- https://bugs.launchpad.net/qemu/+bug/812398 https://gitlab.com/qemu-project/qemu/-/issues/86 2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html message id: 20211119134431.406753-1-farosas@linux.ibm.com Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211130230123.781844-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Use helper_todouble/tosingle in helper_xststdcspRichard Henderson1-11/+10
When computing the predicate "is this value currently formatted for single precision", we do not want to round the value according to the current rounding mode, nor perform a floating-point equality. We want to see if the N bits that make up single-precision are the only ones set within the register, and then a bitwise equality. Fixes a bug in which a single-precision NaN is considered !SP, because float64_eq(nan, nan) is always false. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-35-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update fres to new flags and float64r32Richard Henderson1-10/+10
There is no double-rounding bug here, because the result is merely an estimate to within 1 part in 256, but perform the operation with float64r32_div for consistency. Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-34-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helper for frsqrtesRichard Henderson3-2/+21
There is no double-rounding bug here, because the result is merely an estimate to within 1 part in 32, but perform the operation with float64r32_div for consistency. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-33-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helper for fmulsRichard Henderson3-7/+17
Use float64r32_mul. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helpers for fadds, fsubs, fdivsRichard Henderson3-7/+47
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helper for fsqrtsRichard Henderson3-2/+14
Use float64r32_sqrt. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-30-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Add helpers for fmadds et alRichard Henderson3-9/+25
Use float64r32_muladd. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-29-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update fre to new flagsRichard Henderson1-13/+8
Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-27-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update xsrqpi and xsrqpxp to new flagsRichard Henderson1-10/+5
Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-26-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Update sqrt for new flagsRichard Henderson1-47/+25
Now that vxsqrt and vxsnan are computed directly by softfloat, we don't need to recompute it. Split out float_invalid_op_sqrt to be used in several places. This fixes VSX_SQRT, which did not order its tests correctly to eliminate NaN with sign set. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-25-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17target/ppc: Use helper_todouble in do_frspRichard Henderson1-1/+1
We only needed one ieee arithmetic operation to raise exceptions. To convert back to register form, we can use our simpler non-arithmetic function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211119160502.17432-24-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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