riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-05-26	target/ppc: Implement lwsync with weaker memory ordering	Nicholas Piggin	1	-6/+7
2022-05-09	disas: Remove old libopcode ppc disassembler	Thomas Huth	1	-2/+0
2022-05-05	target/ppc: Remove msr_hv macro	Víctor Colombo	1	-2/+4
2022-05-05	target/ppc: Remove msr_ee macro	Víctor Colombo	1	-5/+10
2022-05-05	target/ppc: Remove msr_le macro	Víctor Colombo	1	-1/+1
2022-05-05	target/ppc: Remove msr_pr macro	Víctor Colombo	1	-2/+2
2022-04-20	target/ppc: Add two missing register callbacks on POWER10	Frederic Barrat	1	-0/+2
2022-04-06	Replace TARGET_WORDS_BIGENDIAN	Marc-André Lureau	1	-1/+1
2022-03-02	target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions	Daniel Henrique Barboza	1	-0/+4
2022-03-02	target/ppc: make power8-pmu.c CONFIG_TCG only	Daniel Henrique Barboza	1	-9/+7
2022-02-18	target/ppc: Move common SPR functions out of cpu_init	Fabiano Rosas	1	-400/+0
2022-02-18	target/ppc: cpu_init: Move check_pow and QOM macros to a header	Fabiano Rosas	1	-37/+0
2022-02-18	target/ppc: cpu_init: Move SPR registration macros to a header	Fabiano Rosas	1	-56/+9
2022-02-18	target/ppc: cpu_init: Expose some SPR registration helpers	Fabiano Rosas	1	-7/+7
2022-02-18	target/ppc: Rename spr_tcg.h to spr_common.h	Fabiano Rosas	1	-1/+1
2022-02-18	target/ppc: cpu_init: Remove register_usprg3_sprs	Fabiano Rosas	1	-10/+11
2022-02-18	target/ppc: cpu_init: Rename register_ne_601_sprs	Fabiano Rosas	1	-21/+20
2022-02-18	target/ppc: cpu_init: Reuse init_proc_745 for the 755	Fabiano Rosas	1	-17/+1
2022-02-18	target/ppc: cpu_init: Reuse init_proc_604 for the 604e	Fabiano Rosas	1	-11/+1
2022-02-18	target/ppc: cpu_init: Reuse init_proc_603 for the e300	Fabiano Rosas	1	-58/+46
2022-02-18	target/ppc: cpu_init: Move 604e SPR registration into a function	Fabiano Rosas	1	-19/+24
2022-02-18	target/ppc: cpu_init: Move e300 SPR registration into a function	Fabiano Rosas	1	-29/+35
2022-02-18	target/ppc: cpu_init: Move 755 L2 cache SPRs into a function	Fabiano Rosas	1	-9/+15
2022-02-18	target/ppc: cpu_init: Deduplicate 7xx SPR registration	Fabiano Rosas	1	-57/+11
2022-02-18	target/ppc: cpu_init: Deduplicate 745/755 SPR registration	Fabiano Rosas	1	-31/+19
2022-02-18	target/ppc: cpu_init: Deduplicate 604 SPR registration	Fabiano Rosas	1	-10/+7
2022-02-18	target/ppc: cpu_init: Deduplicate 603 SPR registration	Fabiano Rosas	1	-19/+9
2022-02-18	target/ppc: cpu_init: Deduplicate 440 SPR registration	Fabiano Rosas	1	-74/+26
2022-02-18	target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx	Fabiano Rosas	1	-16/+91
2022-02-18	target/ppc: cpu_init: Decouple G2 SPR registration from 755	Fabiano Rosas	1	-5/+20
2022-02-18	target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs	Fabiano Rosas	1	-19/+22
2022-02-18	target/ppc: cpu_init: Move 405 SPRs into register_405_sprs	Fabiano Rosas	1	-11/+13
2022-02-18	target/ppc: cpu_init: Avoid nested SPR register functions	Fabiano Rosas	1	-3/+3
2022-02-18	target/ppc: cpu_init: Move Timebase registration into the common function	Fabiano Rosas	1	-80/+18
2022-02-18	target/ppc: cpu_init: Group registration of generic SPRs	Fabiano Rosas	1	-26/+32
2022-02-18	target/ppc: cpu_init: Remove G2LE init code	Fabiano Rosas	1	-41/+1
2022-02-18	target/ppc: cpu_init: Remove not implemented comments	Fabiano Rosas	1	-329/+253
2022-02-09	target/ppc: Merge 7x5 and 7x0 exception model IDs	Fabiano Rosas	1	-8/+8
2022-02-09	target/ppc: Merge exception model IDs for 6xx CPUs	Fabiano Rosas	1	-9/+9
2022-02-09	target/ppc: Remove PowerPC 601 CPUs	Cédric Le Goater	1	-213/+1
2022-02-09	target/ppc: Remove 440x4 CPU	Fabiano Rosas	1	-83/+0
2022-01-28	target/ppc: Remove support for the PowerPC 602 CPU	Cédric Le Goater	1	-147/+0
2022-01-28	target/ppc: 405: Add missing MSR_ME bit	Fabiano Rosas	1	-0/+1
2022-01-28	target/ppc: 405: Rename MSR_POW to MSR_WE	Fabiano Rosas	1	-1/+1
2022-01-12	target/ppc: Add extra float instructions to POWER5P processors	Cédric Le Goater	1	-0/+1
2022-01-12	target/ppc: Add popcntb instruction to POWER5+ processors	Cédric Le Goater	1	-0/+1
2022-01-04	target/ppc: Cache per-pmc insn and cycle count settings	Richard Henderson	1	-0/+1
2022-01-04	ppc/ppc405: Dump specific registers	Cédric Le Goater	1	-6/+21
2022-01-04	ppc/ppc405: Introduce a store helper for SPR_40x_PID	Cédric Le Goater	1	-1/+1
2022-01-04	ppc/ppc405: Restore TCR and STR write handlers	Cédric Le Goater	1	-2/+2