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openrisc
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translate.c
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Author
Files
Lines
2022-04-20
exec/translator: Pass the locked filepointer to disas_log hook
Richard Henderson
1
-3
/
+4
2021-10-15
target/openrisc: Drop checks for singlestep_enabled
Richard Henderson
1
-15
/
+3
2021-09-14
accel/tcg: Add DisasContextBase argument to translator_ld*
Ilya Leoshkevich
1
-1
/
+1
2021-07-21
accel/tcg: Remove TranslatorOps.breakpoint_check
Richard Henderson
1
-17
/
+0
2021-07-13
target/openrisc: Use dc->zero in gen_add, gen_addc
Richard Henderson
1
-5
/
+5
2021-07-13
target/openrisc: Cache constant 0 in DisasContext
Richard Henderson
1
-6
/
+6
2021-07-13
target/openrisc: Use tcg_constant_tl for dc->R0
Richard Henderson
1
-8
/
+2
2021-07-13
target/openrisc: Use tcg_constant_*
Richard Henderson
1
-33
/
+9
2021-07-09
target/openrisc: Use translator_use_goto_tb
Richard Henderson
1
-7
/
+8
2021-07-09
tcg: Avoid including 'trace-tcg.h' in target translate.c
Philippe Mathieu-Daudé
1
-1
/
+0
2021-04-01
target/openrisc: fix icount handling for timer instructions
Pavel Dovgalyuk
1
-0
/
+15
2020-08-21
meson: target
Paolo Bonzini
1
-1
/
+1
2020-08-21
meson: rename included C source files to .c.inc
Paolo Bonzini
1
-1
/
+1
2020-01-15
tcg: Search includes from the project root source directory
Philippe Mathieu-Daudé
1
-1
/
+1
2019-10-28
target/openrisc: fetch code with translator_ld
Emilio G. Cota
1
-1
/
+1
2019-09-04
target/openrisc: Implement l.adrp
Richard Henderson
1
-0
/
+13
2019-09-04
target/openrisc: Implement unordered fp comparisons
Richard Henderson
1
-0
/
+85
2019-09-04
target/openrisc: Add support for ORFPX64A32
Richard Henderson
1
-0
/
+230
2019-09-04
target/openrisc: Check CPUCFG_OF32S for float insns
Richard Henderson
1
-49
/
+35
2019-09-04
target/openrisc: Cache R0 in DisasContext
Richard Henderson
1
-7
/
+12
2019-09-04
target/openrisc: Replace cpu register array with a function
Richard Henderson
1
-97
/
+116
2019-09-04
target/openrisc: Add DisasContext parameter to check_r0_write
Richard Henderson
1
-47
/
+49
2019-09-03
tcg: TCGMemOp is now accelerator independent MemOp
Tony Nguyen
1
-2
/
+2
2019-06-12
Include qemu-common.h exactly where needed
Markus Armbruster
1
-1
/
+0
2019-04-24
tcg: Hoist max_insns computation to tb_gen_code
Richard Henderson
1
-2
/
+2
2019-04-18
qom/cpu: Simplify how CPUClass:cpu_dump_state() prints
Markus Armbruster
1
-6
/
+5
2019-01-30
target/openrisc: Fix LGPL version number
Thomas Huth
1
-1
/
+1
2018-10-31
decodetree: Remove "insn" argument from trans_* expanders
Richard Henderson
1
-100
/
+100
2018-07-03
target/openrisc: Fix cpu_mmu_index
Richard Henderson
1
-1
/
+1
2018-07-03
target/openrisc: Form the spr index from tcg
Richard Henderson
1
-7
/
+9
2018-07-03
target/openrisc: Exit the TB after l.mtspr
Richard Henderson
1
-1
/
+16
2018-07-03
target/openrisc: Split out is_user
Richard Henderson
1
-15
/
+12
2018-07-03
target/openrisc: Link more translation blocks
Richard Henderson
1
-41
/
+55
2018-07-03
target/openrisc: Fix singlestep_enabled
Richard Henderson
1
-18
/
+17
2018-07-03
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
Richard Henderson
1
-3
/
+3
2018-07-03
target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
Richard Henderson
1
-4
/
+0
2018-07-03
target/openrisc: Add print_insn_or1k
Richard Henderson
1
-114
/
+0
2018-06-01
tcg: Pass tb and index to tcg_gen_exit_tb separately
Richard Henderson
1
-3
/
+3
2018-05-14
target/openrisc: Merge disas_openrisc_insn
Richard Henderson
1
-9
/
+4
2018-05-14
target/openrisc: Convert dec_float
Richard Henderson
1
-230
/
+128
2018-05-14
target/openrisc: Convert dec_compi
Richard Henderson
1
-58
/
+58
2018-05-14
target/openrisc: Convert dec_comp
Richard Henderson
1
-62
/
+58
2018-05-14
target/openrisc: Convert dec_M
Richard Henderson
1
-28
/
+13
2018-05-14
target/openrisc: Convert dec_logic
Richard Henderson
1
-36
/
+26
2018-05-14
target/openrisc: Convert dec_mac
Richard Henderson
1
-33
/
+22
2018-05-14
target/openrisc: Convert dec_calc
Richard Henderson
1
-149
/
+173
2018-05-14
target/openrisc: Convert remainder of dec_misc insns
Richard Henderson
1
-149
/
+110
2018-05-14
target/openrisc: Convert memory insns
Richard Henderson
1
-139
/
+136
2018-05-14
target/openrisc: Convert branch insns
Richard Henderson
1
-78
/
+72
2018-05-14
target/openrisc: Start conversion to decodetree.py
Richard Henderson
1
-43
/
+41
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