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author | Richard Henderson <richard.henderson@linaro.org> | 2018-02-19 12:28:12 -0800 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2018-05-14 14:44:26 -0700 |
commit | 7de9729f08043399325e37b26637493313b4543d (patch) | |
tree | 9cd7b7298048cc8a58b1339da25a0f8f536ca4de /target/openrisc/translate.c | |
parent | 4e2d30079c0e771d2c6a607001a4165f2cb51d82 (diff) | |
download | qemu-7de9729f08043399325e37b26637493313b4543d.zip qemu-7de9729f08043399325e37b26637493313b4543d.tar.gz qemu-7de9729f08043399325e37b26637493313b4543d.tar.bz2 |
target/openrisc: Start conversion to decodetree.py
Begin with the 0x08 major opcode, the system instructions.
Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/translate.c')
-rw-r--r-- | target/openrisc/translate.c | 84 |
1 files changed, 41 insertions, 43 deletions
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 586c85d..a4b67f9 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "exec/gen-icount.h" #include "trace-tcg.h" #include "exec/log.h" @@ -51,6 +52,9 @@ typedef struct DisasContext { uint32_t delayed_branch; } DisasContext; +/* Include the auto-generated decoder. */ +#include "decode.inc.c" + static TCGv cpu_sr; static TCGv cpu_R[32]; static TCGv cpu_R0; @@ -65,7 +69,6 @@ static TCGv cpu_lock_value; static TCGv_i32 fpcsr; static TCGv_i64 cpu_mac; /* MACHI:MACLO */ static TCGv_i32 cpu_dflag; -#include "exec/gen-icount.h" void openrisc_translate_init(void) { @@ -1241,46 +1244,41 @@ static void dec_compi(DisasContext *dc, uint32_t insn) } } -static void dec_sys(DisasContext *dc, uint32_t insn) +static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) { - uint32_t op0; - uint32_t K16; - - op0 = extract32(insn, 16, 10); - K16 = extract32(insn, 0, 16); - - switch (op0) { - case 0x000: /* l.sys */ - LOG_DIS("l.sys %d\n", K16); - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_SYSCALL); - dc->base.is_jmp = DISAS_NORETURN; - break; - - case 0x100: /* l.trap */ - LOG_DIS("l.trap %d\n", K16); - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_TRAP); - dc->base.is_jmp = DISAS_NORETURN; - break; + LOG_DIS("l.sys %d\n", a->k); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_SYSCALL); + dc->base.is_jmp = DISAS_NORETURN; + return true; +} - case 0x300: /* l.csync */ - LOG_DIS("l.csync\n"); - break; +static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) +{ + LOG_DIS("l.trap %d\n", a->k); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_TRAP); + dc->base.is_jmp = DISAS_NORETURN; + return true; +} - case 0x200: /* l.msync */ - LOG_DIS("l.msync\n"); - tcg_gen_mb(TCG_MO_ALL); - break; +static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn) +{ + LOG_DIS("l.msync\n"); + tcg_gen_mb(TCG_MO_ALL); + return true; +} - case 0x270: /* l.psync */ - LOG_DIS("l.psync\n"); - break; +static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn) +{ + LOG_DIS("l.psync\n"); + return true; +} - default: - gen_illegal_exception(dc); - break; - } +static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) +{ + LOG_DIS("l.csync\n"); + return true; } static void dec_float(DisasContext *dc, uint32_t insn) @@ -1506,19 +1504,19 @@ static void dec_float(DisasContext *dc, uint32_t insn) static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) { uint32_t op0; - uint32_t insn; - insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); - op0 = extract32(insn, 26, 6); + uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); + /* Transition to the auto-generated decoder. */ + if (decode(dc, insn)) { + return; + } + + op0 = extract32(insn, 26, 6); switch (op0) { case 0x06: dec_M(dc, insn); break; - case 0x08: - dec_sys(dc, insn); - break; - case 0x2e: dec_logic(dc, insn); break; |