riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-12-19	migration: Replace migration's JSON writer by the general one	Markus Armbruster	1	-1/+1
2019-09-04	target/openrisc: Implement move to/from FPCSR	Richard Henderson	1	-0/+11
2019-08-16	Include hw/boards.h a bit less	Markus Armbruster	1	-1/+0
2019-08-16	Include hw/hw.h exactly where needed	Markus Armbruster	1	-1/+0
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-05-08	target/openrisc: Fix LGPL information in the file headers	Thomas Huth	1	-1/+1
2018-11-27	vmstate: constify VMStateField	Marc-André Lureau	1	-2/+3
2018-07-03	target/openrisc: Increase the TLB size	Richard Henderson	1	-3/+2
2018-07-03	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson	1	-2/+2
2018-07-03	target/openrisc: Reduce tlb to a single dimension	Richard Henderson	1	-4/+2
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	1	-26/+0
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	1	-9/+6
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne	1	-1/+0
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	1	-0/+1
2017-05-04	target/openrisc: Implement full vmstate serialization	Stafford Horne	1	-2/+71
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne	1	-3/+3
2017-02-14	target/openrisc: Tidy ppc/npc implementation	Richard Henderson	1	-3/+2
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	1	-2/+3
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	1	-1/+37
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson	1	-8/+16
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+54