aboutsummaryrefslogtreecommitdiff
path: root/target/openrisc/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2021-11-02target/openrisc: Make openrisc_cpu_tlb_fill sysemu onlyRichard Henderson1-1/+1
2021-09-14target/openrisc: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-1/+1
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson1-1/+1
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé1-1/+1
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé1-0/+8
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-4/+13
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2020-12-15target/openrisc: Move pic_cpu code into CPU object properPeter Maydell1-0/+32
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell1-4/+4
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz1-2/+1
2019-09-04target/openrisc: Update cpu "any" to v1.3Richard Henderson1-1/+1
2019-09-04target/openrisc: Implement move to/from FPCSRRichard Henderson1-0/+1
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson1-1/+1
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson1-1/+1
2019-09-04target/openrisc: Add VR2 and AVR special processor registersRichard Henderson1-2/+6
2019-09-04target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson1-7/+16
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson1-2/+1
2019-05-10target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson1-3/+2
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster1-10/+5
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth1-1/+1
2018-07-03linux-user: Implement signals for openriscRichard Henderson1-0/+1
2018-07-03target/openrisc: Increase the TLB sizeRichard Henderson1-2/+4
2018-07-03target/openrisc: Remove indirect function calls for mmuRichard Henderson1-4/+0
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson1-0/+6
2018-06-01target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé1-1/+0
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-3/+2
2017-10-27openrisc: cleanup cpu type name compositionIgor Mammedov1-46/+23
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-6/+1
2017-10-21openrisc/cputimer: Perparation for MulticoreStafford Horne1-1/+0
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé1-4/+0
2017-09-01openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov1-5/+0
2017-05-04target/openrisc: Support non-busy idle state using PMR SPRStafford Horne1-1/+2
2017-05-04target/openrisc: Remove duplicate features propertyStafford Horne1-14/+3
2017-05-04target/openrisc: implement shadow registersStafford Horne1-1/+3
2017-04-21target/openrisc: Implement EVBAR registerTim 'mithro' Ansell1-0/+2
2017-02-14target/openrisc: Implement lwa, swaRichard Henderson1-0/+1
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée1-8/+1
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+278