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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 15:23:42 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:51:19 -0700 |
| commit | 8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2 (patch) | |
| tree | 91f063efef1666667185b148b2a33259783f37d8 /target/openrisc/cpu.c | |
| parent | c7efab4fc1fe5092136305a2cae67fca03f4f9c5 (diff) | |
| download | qemu-8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2.zip qemu-8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2.tar.gz qemu-8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2.tar.bz2 | |
target/openrisc: Add VR2 and AVR special processor registers
Update the CPUCFG bits to arch v1.3.
Include support for AVRP for cpu "any".
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index d9f447e..9f566ad 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -126,9 +126,13 @@ static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu = OPENRISC_CPU(obj); - cpu->env.vr = 0x13000000; + cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ + cpu->env.vr2 = 0; /* No version specific id */ + cpu->env.avr = 0x01010000; /* Architecture v1.1 */ + cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; + cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | + CPUCFGR_AVRP | CPUCFGR_EVBARP; /* 1Way, TLB_SIZE entries. */ cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) |