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2021-02-18target/mips: Create mips_io_recompile_replay_branchRichard Henderson1-0/+18
2021-02-16sev/i386: Don't allow a system reset under an SEV-ES guestTom Lendacky1-0/+5
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-13/+23
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+2
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-1/+3
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana1-2/+2
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost1-1/+3
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2021-01-14target/mips: Remove vendor specific CPU definitionsPhilippe Mathieu-Daudé2-10/+7
2021-01-14target/mips: Remove CPU_NANOMIPS32 definitionPhilippe Mathieu-Daudé2-5/+2
2021-01-14target/mips: Remove CPU_R5900 definitionPhilippe Mathieu-Daudé1-1/+0
2021-01-14target/mips: Convert Rel6 LL/SC opcodes to decodetreePhilippe Mathieu-Daudé2-2/+2
2021-01-14target/mips: Convert Rel6 LLD/SCD opcodes to decodetreePhilippe Mathieu-Daudé2-2/+3
2021-01-14target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetreePhilippe Mathieu-Daudé2-4/+8
2021-01-14target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetreePhilippe Mathieu-Daudé2-4/+5
2021-01-14target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetreePhilippe Mathieu-Daudé2-4/+6
2021-01-14target/mips: Convert Rel6 CACHE/PREF opcodes to decodetreePhilippe Mathieu-Daudé2-2/+3
2021-01-14target/mips: Convert Rel6 COP1X opcode to decodetreePhilippe Mathieu-Daudé2-1/+2
2021-01-14target/mips: Convert Rel6 Special2 opcode to decodetreePhilippe Mathieu-Daudé3-2/+9
2021-01-14target/mips: Remove now unreachable LSA/DLSA opcodes codePhilippe Mathieu-Daudé1-23/+5
2021-01-14target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodesPhilippe Mathieu-Daudé6-0/+80
2021-01-14target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodesPhilippe Mathieu-Daudé4-0/+37
2021-01-14target/mips: Extract LSA/DLSA translation generatorsPhilippe Mathieu-Daudé4-32/+71
2021-01-14target/mips: Use decode_ase_msa() generated from decodetreePhilippe Mathieu-Daudé3-62/+11
2021-01-14target/mips: Introduce decode tree bindings for MSA ASEPhilippe Mathieu-Daudé4-0/+68
2021-01-14target/mips: Pass TCGCond argument to MSA gen_check_zero_element()Philippe Mathieu-Daudé1-6/+4
2021-01-14target/mips: Extract MSA translation routinesPhilippe Mathieu-Daudé3-2249/+2266
2021-01-14target/mips: Declare gen_msa/_branch() in 'translate.h'Philippe Mathieu-Daudé2-2/+4
2021-01-14target/mips: Extract MSA helper definitionsPhilippe Mathieu-Daudé2-434/+445
2021-01-14target/mips: Extract MSA helpers from op_helper.cPhilippe Mathieu-Daudé2-394/+393
2021-01-14target/mips: Move msa_reset() to msa_helper.cPhilippe Mathieu-Daudé4-36/+39
2021-01-14target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()Philippe Mathieu-Daudé1-21/+48
2021-01-14target/mips: Remove CPUMIPSState* argument from gen_msa*() methodsPhilippe Mathieu-Daudé1-29/+28
2021-01-14target/mips: Extract msa_translate_init() from mips_tcg_init()Philippe Mathieu-Daudé2-13/+21
2021-01-14target/mips: Alias MSA vector registers on FPU scalar registersPhilippe Mathieu-Daudé1-5/+9
2021-01-14target/mips: Remove now unused ASE_MSA definitionPhilippe Mathieu-Daudé2-5/+4
2021-01-14target/mips: Simplify MSA TCG logicPhilippe Mathieu-Daudé1-12/+11
2021-01-14target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSAPhilippe Mathieu-Daudé1-1/+1
2021-01-14target/mips: Simplify msa_reset()Philippe Mathieu-Daudé2-4/+5
2021-01-14target/mips: Introduce ase_msa_available() helperPhilippe Mathieu-Daudé4-11/+15
2021-01-14target/mips/translate: Expose check_mips_64() to 32-bit modePhilippe Mathieu-Daudé2-7/+3
2021-01-14target/mips/translate: Extract decode_opc_legacy() from decode_opc()Philippe Mathieu-Daudé1-20/+29
2021-01-14target/mips: Only build TCG code when CONFIG_TCG is setPhilippe Mathieu-Daudé1-2/+6
2021-01-14target/mips: Extract FPU specific definitions to translate.hPhilippe Mathieu-Daudé2-70/+71
2021-01-14target/mips: Declare generic FPU / Coprocessor functions in translate.hPhilippe Mathieu-Daudé2-12/+24
2021-01-14target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instructionPhilippe Mathieu-Daudé2-362/+368
2021-01-14target/mips: Replace gen_exception_err(err=0) by gen_exception_end()Philippe Mathieu-Daudé1-3/+3
2021-01-14target/mips/translate: Add declarations for generic codePhilippe Mathieu-Daudé2-38/+57
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