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author | Claudio Fontana <cfontana@suse.de> | 2021-02-04 17:39:23 +0100 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:15 -1000 |
commit | 78271684719f34c1cc19f895e089f2f19b69698d (patch) | |
tree | 5f47406eb8c2be4e37e411e5053678e4d91e09d3 /target/mips | |
parent | c73bdb35a91fb6b17c2c93b1ba381fc88a406f8d (diff) | |
download | qemu-78271684719f34c1cc19f895e089f2f19b69698d.zip qemu-78271684719f34c1cc19f895e089f2f19b69698d.tar.gz qemu-78271684719f34c1cc19f895e089f2f19b69698d.tar.bz2 |
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r-- | target/mips/cpu.c | 36 |
1 files changed, 23 insertions, 13 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1e93e29..ad163ea 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -663,6 +663,26 @@ static Property mips_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +/* + * NB: cannot be const, as some elements are changed for specific + * mips hardware (see hw/mips/jazz.c). + */ +static struct TCGCPUOps mips_tcg_ops = { + .initialize = mips_tcg_init, + .synchronize_from_tb = mips_cpu_synchronize_from_tb, + .cpu_exec_interrupt = mips_cpu_exec_interrupt, + .tlb_fill = mips_cpu_tlb_fill, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt = mips_cpu_do_interrupt, + .do_transaction_failed = mips_cpu_do_transaction_failed, + .do_unaligned_access = mips_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; +#endif /* CONFIG_TCG */ + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -685,21 +705,11 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->vmsd = &vmstate_mips_cpu; #endif cc->disas_set_info = mips_cpu_disas_set_info; -#ifdef CONFIG_TCG - cc->tcg_ops.initialize = mips_tcg_init; - cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt; - cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb; - cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill; -#ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed; - cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access; - -#endif /* CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - cc->gdb_num_core_regs = 73; cc->gdb_stop_before_watchpoint = true; +#ifdef CONFIG_TCG + cc->tcg_ops = &mips_tcg_ops; +#endif /* CONFIG_TCG */ } static const TypeInfo mips_cpu_type_info = { |