diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2021-02-13 13:03:14 +0000 |
---|---|---|
committer | Alex Bennée <alex.bennee@linaro.org> | 2021-02-18 08:19:15 +0000 |
commit | 95ab7c22914af17023421caf157360a9a3419007 (patch) | |
tree | 5f660d74cb96d16a5cc2785b54e60045efc8e14c /target/mips | |
parent | d9bcb58a128344b87a26d6073caa2c6117ec211d (diff) | |
download | qemu-95ab7c22914af17023421caf157360a9a3419007.zip qemu-95ab7c22914af17023421caf157360a9a3419007.tar.gz qemu-95ab7c22914af17023421caf157360a9a3419007.tar.bz2 |
target/mips: Create mips_io_recompile_replay_branch
Move the code from accel/tcg/translate-all.c to target/mips/cpu.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210208233906.479571-4-richard.henderson@linaro.org>
Message-Id: <20210213130325.14781-13-alex.bennee@linaro.org>
Diffstat (limited to 'target/mips')
-rw-r--r-- | target/mips/cpu.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ad163ea..bf70c77 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -268,6 +268,23 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } + +# ifndef CONFIG_USER_ONLY +static bool mips_io_recompile_replay_branch(CPUState *cs, + const TranslationBlock *tb) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) != 0 + && env->active_tc.PC != tb->pc) { + env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &= ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} +# endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ static bool mips_cpu_has_work(CPUState *cs) @@ -679,6 +696,7 @@ static struct TCGCPUOps mips_tcg_ops = { .do_interrupt = mips_cpu_do_interrupt, .do_transaction_failed = mips_cpu_do_transaction_failed, .do_unaligned_access = mips_cpu_do_unaligned_access, + .io_recompile_replay_branch = mips_io_recompile_replay_branch, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ |