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AgeCommit message (Expand)AuthorFilesLines
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau2-7/+7
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau3-29/+29
2022-03-29target/mips: Fix address space range declaration on n32WANG Xuerui1-1/+1
2022-03-09Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into stagingPeter Maydell3-19/+10
2022-03-07target/mips: Remove duplicated MIPSCPU::cp0_count_ratePhilippe Mathieu-Daudé3-19/+9
2022-03-07target/mips: Fix cycle counter timing calculationsSimon Burge1-1/+2
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2-4/+1
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-4/+2
2022-03-06target: Use forward declared type instead of structure typePhilippe Mathieu-Daudé1-7/+7
2022-03-06target: Include missing 'cpu.h'Philippe Mathieu-Daudé1-0/+1
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé3-0/+3
2022-01-11target/mips: Extract trap code into env->error_codeRichard Henderson3-8/+24
2022-01-11target/mips: Extract break code into env->error_codeRichard Henderson4-5/+16
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot3-38/+38
2021-11-02Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into stagingRichard Henderson4-2087/+845
2021-11-02target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPUPhilippe Mathieu-Daudé1-1/+0
2021-11-02target/mips: Fix Loongson-3A4000 MSAIR config registerPhilippe Mathieu-Daudé1-0/+1
2021-11-02target/mips: Remove one MSA unnecessary decodetree overlap groupPhilippe Mathieu-Daudé1-182/+180
2021-11-02target/mips: Remove generic MSA opcodePhilippe Mathieu-Daudé2-9/+0
2021-11-02target/mips: Convert CTCMSA opcode to decodetreePhilippe Mathieu-Daudé2-58/+16
2021-11-02target/mips: Convert CFCMSA opcode to decodetreePhilippe Mathieu-Daudé2-9/+23
2021-11-02target/mips: Convert MSA MOVE.V opcode to decodetreePhilippe Mathieu-Daudé2-6/+20
2021-11-02target/mips: Convert MSA COPY_S and INSERT opcodes to decodetreePhilippe Mathieu-Daudé2-88/+19
2021-11-02target/mips: Convert MSA COPY_U opcode to decodetreePhilippe Mathieu-Daudé2-26/+41
2021-11-02target/mips: Convert MSA ELM instruction format to decodetreePhilippe Mathieu-Daudé2-13/+52
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)Philippe Mathieu-Daudé2-863/+106
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)Philippe Mathieu-Daudé2-34/+9
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)Philippe Mathieu-Daudé2-158/+35
2021-11-02target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)Philippe Mathieu-Daudé2-12/+11
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)Philippe Mathieu-Daudé2-176/+76
2021-11-02target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)Philippe Mathieu-Daudé2-39/+38
2021-11-02target/mips: Convert MSA VEC instruction format to decodetreePhilippe Mathieu-Daudé2-75/+31
2021-11-02target/mips: Convert MSA 2R instruction format to decodetreePhilippe Mathieu-Daudé2-75/+19
2021-11-02target/mips: Convert MSA FILL opcode to decodetreePhilippe Mathieu-Daudé2-12/+21
2021-11-02target/mips: Convert MSA 2RF instruction format to decodetreePhilippe Mathieu-Daudé2-85/+53
2021-11-02target/mips: Convert MSA load/store instruction format to decodetreePhilippe Mathieu-Daudé2-59/+36
2021-11-02target/mips: Convert MSA I8 instruction format to decodetreePhilippe Mathieu-Daudé2-56/+27
2021-11-02target/mips: Convert MSA SHF opcode to decodetreePhilippe Mathieu-Daudé2-17/+22
2021-11-02target/mips: Convert MSA BIT instruction format to decodetreePhilippe Mathieu-Daudé2-97/+101
2021-11-02target/mips: Convert MSA I5 instruction format to decodetreePhilippe Mathieu-Daudé2-77/+41
2021-11-02target/mips: Convert MSA LDI opcode to decodetreePhilippe Mathieu-Daudé2-9/+21
2021-11-02target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_vPhilippe Mathieu-Daudé2-18/+17
2021-11-02target/mips: Use enum definitions from CPUMIPSMSADataFormat enumPhilippe Mathieu-Daudé1-3/+3
2021-11-02target/mips: Have check_msa_access() return a booleanPhilippe Mathieu-Daudé1-7/+18
2021-11-02target/mips: Use dup_const() to simplifyPhilippe Mathieu-Daudé1-20/+3
2021-11-02target/mips: Adjust style in msa_translate_init()Philippe Mathieu-Daudé1-1/+3
2021-11-02target/mips: Fix MSA MSUBV.B opcodePhilippe Mathieu-Daudé1-16/+16