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author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-23 09:57:16 +0200 |
---|---|---|
committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
commit | 340ee8b3f1872c7f8969a5eb48fc3b5a9284e27b (patch) | |
tree | f99393c7357bc24f05ea56befa2bc756e2f7bc3b /target/mips | |
parent | 40f75c02d4c796cb54826b65edd2e2530e5129f8 (diff) | |
download | qemu-340ee8b3f1872c7f8969a5eb48fc3b5a9284e27b.zip qemu-340ee8b3f1872c7f8969a5eb48fc3b5a9284e27b.tar.gz qemu-340ee8b3f1872c7f8969a5eb48fc3b5a9284e27b.tar.bz2 |
target/mips: Have check_msa_access() return a boolean
Have check_msa_access() return a boolean value so we can
return early if MSA is not enabled (the instruction got
decoded properly, but we raised an exception).
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-6-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
-rw-r--r-- | target/mips/tcg/msa_translate.c | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index b135c58..e0ccd8c 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -295,19 +295,24 @@ void msa_translate_init(void) } } -static inline int check_msa_access(DisasContext *ctx) +/* + * Check if MSA is enabled. + * This function is always called with MSA available. + * If MSA is disabled, raise an exception. + */ +static inline bool check_msa_enabled(DisasContext *ctx) { if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && !(ctx->hflags & MIPS_HFLAG_F64))) { gen_reserved_instruction(ctx); - return 0; + return false; } if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { generate_exception_end(ctx, EXCP_MSADIS); - return 0; + return false; } - return 1; + return true; } static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, @@ -339,7 +344,9 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) { TCGv_i64 t0; - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } if (ctx->hflags & MIPS_HFLAG_BMASK) { gen_reserved_instruction(ctx); @@ -371,7 +378,9 @@ static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) { - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } if (ctx->hflags & MIPS_HFLAG_BMASK) { gen_reserved_instruction(ctx); @@ -2143,7 +2152,9 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) { uint32_t opcode = ctx->opcode; - check_msa_access(ctx); + if (!check_msa_enabled(ctx)) { + return true; + } switch (MASK_MSA_MINOR(opcode)) { case OPC_MSA_I8_00: |