riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-07-12	target/mips: introduce decodetree structure for Cavium Octeon extension	Pavel Dovgalyuk	1	-0/+1
2021-01-14	target/mips: Remove vendor specific CPU definitions	Philippe Mathieu-Daudé	1	-5/+0
2021-01-14	target/mips: Remove CPU_NANOMIPS32 definition	Philippe Mathieu-Daudé	1	-3/+0
2021-01-14	target/mips: Remove CPU_R5900 definition	Philippe Mathieu-Daudé	1	-1/+0
2021-01-14	target/mips: Remove now unused ASE_MSA definition	Philippe Mathieu-Daudé	1	-1/+0
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()	Philippe Mathieu-Daudé	1	-1/+3
2021-01-14	target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1	Philippe Mathieu-Daudé	1	-4/+4
2021-01-14	target/mips/mips-defs: Reorder CPU_MIPS5 definition	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment	Philippe Mathieu-Daudé	1	-6/+0
2020-06-15	target/mips: Add comments for vendor-specific ASEs	Jiaxun Yang	1	-0/+4
2020-06-15	target/mips: Legalize Loongson insn flags	Jiaxun Yang	1	-2/+2
2020-06-09	target/mips: Add Loongson-3 CPU definition	Huacai Chen	1	-20/+25
2019-10-01	target/mips: Clean up mips-defs.h	Aleksandar Markovic	1	-26/+32
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson	1	-15/+0
2018-10-29	target/mips: Define a bit for MXU in insn_flags	Craig Janeczek	1	-0/+1
2018-10-24	target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants	Fredrik Noring	1	-0/+3
2018-10-18	target/mips: Improve DSP R2/R3-related naming	Stefan Markovic	1	-2/+2
2018-10-18	target/mips: Add bit definitions for DSP R3 ASE	Stefan Markovic	1	-0/+1
2018-10-18	target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags)	Philippe Mathieu-Daudé	1	-34/+44
2018-08-24	target/mips: Add preprocessor constants for nanoMIPS	Aleksandar Markovic	1	-0/+4
2017-10-16	linux-user: Tidy and enforce reserved_va initialization	Richard Henderson	1	-1/+5
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+91