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| author | Richard Henderson <rth@twiddle.net> | 2017-10-05 10:36:00 -0400 |
|---|---|---|
| committer | Riku Voipio <riku.voipio@linaro.org> | 2017-10-16 16:00:56 +0300 |
| commit | 18e80c55bb6ec17c05ec0ba717ec83933c2bfc07 (patch) | |
| tree | ad7b346cfad273e9b252ac0ae82cdbc709a3931f /target/mips/mips-defs.h | |
| parent | de258eb07db6cf893ef1bfad8c0cedc0b983db55 (diff) | |
| download | qemu-18e80c55bb6ec17c05ec0ba717ec83933c2bfc07.zip qemu-18e80c55bb6ec17c05ec0ba717ec83933c2bfc07.tar.gz qemu-18e80c55bb6ec17c05ec0ba717ec83933c2bfc07.tar.bz2 | |
linux-user: Tidy and enforce reserved_va initialization
We had a check using TARGET_VIRT_ADDR_SPACE_BITS to make sure
that the allocation coming in from the command-line option was
not too large, but that didn't include target-specific knowledge
about other restrictions on user-space.
Remove several target-specific hacks in linux-user/main.c.
For MIPS and Nios, we can replace them with proper adjustments
to the respective target's TARGET_VIRT_ADDR_SPACE_BITS definition.
For ARM, we had no existing ifdef but I suspect that the current
default value of 0xf7000000 was chosen with this in mind. Define
a workable value in linux-user/arm/, and also document why the
special case is required.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20170708025030.15845-3-rth@twiddle.net>
Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
Diffstat (limited to 'target/mips/mips-defs.h')
| -rw-r--r-- | target/mips/mips-defs.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 047554e..d239069 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -15,7 +15,11 @@ #else #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 40 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +# ifdef CONFIG_USER_ONLY +# define TARGET_VIRT_ADDR_SPACE_BITS 31 +# else +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif #endif /* Masks used to mark instructions to indicate which ISA level they |