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path: root/target/m68k/translate.c
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2018-01-25target/m68k: add pflush/ptestLaurent Vivier1-0/+33
2018-01-25target/m68k: add movesLaurent Vivier1-3/+67
2018-01-25target/m68k: add index parameter to gen_load()/gen_store() and Co.Laurent Vivier1-59/+66
2018-01-25target/m68k: add Transparent TranslationLaurent Vivier1-0/+3
2018-01-25target/m68k: add MC68040 MMULaurent Vivier1-0/+2
2018-01-25target/m68k: fix TCG variable double freeLaurent Vivier1-1/+0
2018-01-08Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request'...Peter Maydell1-101/+396
2018-01-04target/m68k: fix m68k_cpu_dump_state()Laurent Vivier1-3/+6
2018-01-04target/m68k: add the Interrupt Stack PointerLaurent Vivier1-3/+37
2018-01-04target/m68k: add andi/ori/eori to SR/CCRLaurent Vivier1-7/+46
2018-01-04target/m68k: add 680x0 "move to SR" instructionLaurent Vivier1-16/+22
2018-01-04target/m68k: move CCR/SR functionsLaurent Vivier1-56/+55
2018-01-04target/m68k: implement fsave/frestoreLaurent Vivier1-8/+15
2018-01-04target/m68k: add resetLaurent Vivier1-0/+13
2018-01-04target/m68k: add cpush/cinvLaurent Vivier1-0/+20
2018-01-04target/m68k: softmmu cleanupLaurent Vivier1-6/+33
2018-01-04target/m68k: add move16Laurent Vivier1-0/+72
2018-01-04target/m68k: add chk and chk2Laurent Vivier1-1/+76
2018-01-04target/m68k: use insn_pc to generate instruction fault addressLaurent Vivier1-20/+20
2018-01-04target/m68k: fix gen_get_ccr()Laurent Vivier1-1/+0
2018-01-04target-m68k: sync CC_OP before gen_jmp_tb()Laurent Vivier1-1/+2
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-7/+7
2017-12-21target/m68k: fix set_cc_op()Laurent Vivier1-0/+1
2017-12-21target/m68k: remove unused variable gen_throws_exceptionLaurent Vivier1-10/+0
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-5/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/m68k: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-2/+10
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-10-24tcg: Remove TCGV_EQUAL*Richard Henderson1-1/+1
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-1/+6
2017-07-31m68k/translate: fix incorrect copy/pastePhilippe Mathieu-Daudé1-1/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-19target/m68k: optimize bcd_flags() using extract opPhilippe Mathieu-Daudé1-2/+1
2017-06-29target/m68k: add fmovemLaurent Vivier1-30/+63
2017-06-29target/m68k: add explicit single and double precision operations (part 2)Laurent Vivier1-4/+22
2017-06-29target/m68k: add fsglmul and fsgldivLaurent Vivier1-0/+6
2017-06-29target/m68k: add explicit single and double precision operationsLaurent Vivier1-5/+35
2017-06-29target/m68k: add fmovecrLaurent Vivier1-1/+12
2017-06-29target/m68k: add fscc.Laurent Vivier1-79/+131
2017-06-21target-m68k: add FPCR and FPSRLaurent Vivier1-91/+260
2017-06-21target-m68k: use floatx80 internallyLaurent Vivier1-227/+419
2017-06-21target-m68k: move fmove CR to a functionLaurent Vivier1-25/+31
2017-06-15target-m68k: define ext_opsizeLaurent Vivier1-19/+24
2017-06-15target/m68k: fix V flag for CC_OP_SUBxLaurent Vivier1-1/+1
2017-06-07target/m68k: implement rtdLaurent Vivier1-0/+11
2017-01-14target-m68k: increment/decrement with SPLaurent Vivier1-2/+12
2017-01-14target-m68k: CAS doesn't need aligned accessLaurent Vivier1-1/+0
2017-01-14target-m68k: manage pre-dec et post-inc in CASLaurent Vivier1-0/+9
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