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path: root/target/loongarch/insn_trans/trans_privileged.c.inc
AgeCommit message (Expand)AuthorFilesLines
2024-01-06target/loongarch: move translate modules to tcg/Song Gao1-498/+0
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson1-26/+26
2023-08-24target/loongarch: Add avail_IOCSR to check iocsr instructionsSong Gao1-8/+8
2023-08-24target/loongarch: Add avail_LSPW to check LSPW instructionsSong Gao1-0/+8
2023-08-24target/loongarch: Add a check parameter to the TRANS macroSong Gao1-8/+8
2023-07-24target/loongarch: Fix the CSRRD CPUID instruction on big endian hostsThomas Huth1-7/+1
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-3/+1
2023-03-05target/loongarch: Drop tcg_temp_freeRichard Henderson1-4/+0
2023-03-05target/loongarch: Drop temp_newRichard Henderson1-1/+1
2022-11-07target/loongarch: Separate the hardware flags into MMU index and PLVRui Wang1-2/+2
2022-11-04target/loongarch: Adjust the layout of hardware flags bit fieldsRui Wang1-1/+1
2022-07-04target/loongarch: Adjust functions and structure to support user-modeSong Gao1-0/+36
2022-06-06target/loongarch: Add other core instructions supportXiaojuan Yang1-0/+65
2022-06-06target/loongarch: Add TLB instruction supportXiaojuan Yang1-0/+102
2022-06-06target/loongarch: Add LoongArch IOCSR instructionXiaojuan Yang1-0/+35
2022-06-06target/loongarch: Add LoongArch CSR instructionXiaojuan Yang1-0/+264