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AgeCommit message (Expand)AuthorFilesLines
2023-07-08target/i386: Use aesdec_ISB_ISR_IMC_AKRichard Henderson1-10/+6
2023-07-08target/i386: Use aesenc_SB_SR_MC_AKRichard Henderson1-9/+5
2023-07-08target/i386: Use aesdec_IMCRichard Henderson1-8/+3
2023-07-08target/i386: Use aesdec_ISB_ISR_AKRichard Henderson1-5/+5
2023-07-08target/i386: Use aesenc_SB_SR_AKRichard Henderson1-5/+6
2023-07-07target/i386: Add new CPU model GraniteRapidsTao Su1-0/+136
2023-07-07target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapi...Lei Wang1-2/+11
2023-07-07target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIESTao Su1-0/+4
2023-07-07target/i386: Allow MCDT_NO if host supportsTao Su1-0/+4
2023-07-07target/i386: Add support for MCDT_NO in CPUID enumerationTao Su2-0/+30
2023-07-07target/i386: Adjust feature level according to FEAT_7_1_EDXTao Su1-0/+1
2023-06-29Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson2-12/+101
2023-06-29target/i386: emulate 64-bit ring 0 for linux-user if LM feature is setPaolo Bonzini2-4/+17
2023-06-29target/i386: ignore CPL0-specific features in user mode emulationPaolo Bonzini1-7/+76
2023-06-29target/i386: ignore ARCH_CAPABILITIES features in user mode emulationPaolo Bonzini1-0/+7
2023-06-29target/i386: Export MSR_ARCH_CAPABILITIES bits to guestsPawan Gupta1-2/+2
2023-06-28exec/memory: Add symbolic value for memory listener priority for accelIsaku Yamahata3-3/+3
2023-06-28target/i386/WHPX: Fix error message when fail to set ProcessorCountZhao Liu1-2/+2
2023-06-28accel: Rename HVF 'struct hvf_vcpu_state' -> AccelCPUStatePhilippe Mathieu-Daudé8-233/+233
2023-06-28accel: Rename 'cpu_state' -> 'cs'Philippe Mathieu-Daudé2-195/+195
2023-06-28accel: Inline WHPX get_whpx_vcpu()Philippe Mathieu-Daudé1-19/+10
2023-06-28accel: Rename WHPX 'struct whpx_vcpu' -> AccelCPUStatePhilippe Mathieu-Daudé1-15/+15
2023-06-28accel: Remove WHPX unreachable error pathPhilippe Mathieu-Daudé1-6/+0
2023-06-28accel: Inline NVMM get_qemu_vcpu()Philippe Mathieu-Daudé1-17/+11
2023-06-28accel: Rename NVMM 'struct qemu_vcpu' -> AccelCPUStatePhilippe Mathieu-Daudé1-16/+16
2023-06-28accel: Remove NVMM unreachable error pathPhilippe Mathieu-Daudé1-4/+0
2023-06-28accel: Move HAX hThread to accelerator contextPhilippe Mathieu-Daudé4-3/+6
2023-06-28accel: Rename HAX 'struct hax_vcpu_state' -> AccelCPUStatePhilippe Mathieu-Daudé6-18/+19
2023-06-28accel: Rename 'hax_vcpu' as 'accel' in CPUStatePhilippe Mathieu-Daudé4-16/+16
2023-06-28accel: Destroy HAX vCPU threads once donePhilippe Mathieu-Daudé2-0/+4
2023-06-28accel: Fix a leak on Windows HAXPhilippe Mathieu-Daudé1-0/+3
2023-06-28accel: Remove unused hThread variable on TCG/WHPXPhilippe Mathieu-Daudé1-3/+0
2023-06-28accel: Re-enable WHPX cross-build on case sensitive filesystemsPhilippe Mathieu-Daudé2-4/+4
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
2023-06-26target/i386: implement SYSCALL/SYSRET in 32-bit emulatorsPaolo Bonzini6-13/+11
2023-06-26target/i386: implement RDPID in TCGPaolo Bonzini4-13/+44
2023-06-26target/i386: sysret and sysexit are privilegedPaolo Bonzini1-2/+2
2023-06-26target/i386: AMD only supports SYSENTER/SYSEXIT in 32-bit modePaolo Bonzini1-4/+6
2023-06-26target/i386: Intel only supports SYSCALL/SYSRET in long modePaolo Bonzini2-1/+12
2023-06-26target/i386: TCG supports WBNOINVDPaolo Bonzini2-2/+3
2023-06-26target/i386: TCG supports XSAVEERPTRPaolo Bonzini1-1/+3
2023-06-26target/i386: do not accept RDSEED if CPUID bit absentPaolo Bonzini1-0/+8
2023-06-26target/i386: TCG supports RDSEEDPaolo Bonzini1-3/+2
2023-06-26target/i386: TCG supports 3DNow! prefetch(w)Paolo Bonzini1-1/+2
2023-06-26target/i386: fix INVD vmexitPaolo Bonzini1-1/+1
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé7-14/+14
2023-06-20meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé1-1/+1
2023-06-20target/i386: Simplify i386_tr_init_disas_context()Philippe Mathieu-Daudé1-3/+0
2023-06-13target/i386: Rename helper template headers as '.h.inc'Philippe Mathieu-Daudé6-11/+11
2023-06-13target/i386/helper: Shuffle do_cpu_init()Philippe Mathieu-Daudé1-8/+4
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