index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
i386
Age
Commit message (
Expand
)
Author
Files
Lines
2024-05-22
target-i386: hyper-v: Correct kvm_hv_handle_exit return value
donsheng
1
-1
/
+1
2024-05-22
i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 2...
Zhao Liu
1
-9
/
+1
2024-05-22
i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4]
Zhao Liu
2
-43
/
+56
2024-05-22
i386: Add cache topology info in CPUCacheInfo
Zhao Liu
2
-0
/
+43
2024-05-22
i386/cpu: Introduce module-id to X86CPU
Zhao Liu
2
-0
/
+3
2024-05-22
i386: Expose module level in CPUID[0x1F]
Zhao Liu
2
-0
/
+7
2024-05-22
i386: Support modules_per_die in X86CPUTopoInfo
Zhao Liu
1
-5
/
+8
2024-05-22
i386: Introduce module level cpu topology to CPUX86State
Zhao Liu
2
-0
/
+4
2024-05-22
i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level
Zhao Liu
1
-25
/
+110
2024-05-22
i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB]
Zhao Liu
2
-11
/
+16
2024-05-22
i386/cpu: Introduce bitmap to cache available CPU topology levels
Zhao Liu
3
-4
/
+21
2024-05-22
i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()
Zhao Liu
1
-13
/
+18
2024-05-22
i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits...
Zhao Liu
1
-4
/
+4
2024-05-22
i386/cpu: Use APIC ID info to encode cache topo in CPUID[4]
Zhao Liu
1
-10
/
+40
2024-05-22
i386/cpu: Fix i/d-cache topology to core level for Intel CPU
Zhao Liu
1
-2
/
+4
2024-05-22
target/i386: add control bits support for LAM
Binbin Wu
2
-1
/
+10
2024-05-22
target/i386: add support for LAM in CPUID enumeration
Robert Hoo
2
-1
/
+3
2024-05-22
target/i386: clean up AAM/AAD
Paolo Bonzini
4
-19
/
+16
2024-05-22
target/i386: generate simpler code for ROL/ROR with immediate count
Paolo Bonzini
1
-12
/
+14
2024-05-15
target/i386: Use translator_ldub for everything
Richard Henderson
1
-5
/
+3
2024-05-15
accel/tcg: Provide default implementation of disas_log
Richard Henderson
1
-11
/
+0
2024-05-10
i386: select correct components for no-board build
Paolo Bonzini
1
-0
/
+1
2024-05-10
target/i386: fix feature dependency for WAITPKG
Paolo Bonzini
1
-2
/
+2
2024-05-10
target/i386: move prefetch and multi-byte UD/NOP to new decoder
Paolo Bonzini
4
-33
/
+27
2024-05-10
target/i386: rdpkru/wrpkru are no-prefix instructions
Paolo Bonzini
1
-2
/
+4
2024-05-10
target/i386: fix operand size for DATA16 REX.W POPCNT
Paolo Bonzini
1
-16
/
+1
2024-05-10
target/i386: remove PCOMMIT from TCG, deprecate property
Paolo Bonzini
3
-14
/
+2
2024-05-09
misc: Use QEMU header path relative to include/ directory
Philippe Mathieu-Daudé
1
-1
/
+1
2024-05-07
target/i386: remove duplicate prefix decoding
Paolo Bonzini
2
-219
/
+103
2024-05-07
target/i386: split legacy decoder into a separate function
Paolo Bonzini
1
-21
/
+37
2024-05-07
target/i386: decode x87 instructions in a separate function
Paolo Bonzini
1
-554
/
+566
2024-05-07
target/i386: remove now-converted opcodes from old decoder
Paolo Bonzini
5
-2320
/
+11
2024-05-07
target/i386: port extensions of one-byte opcodes to new decoder
Paolo Bonzini
3
-0
/
+39
2024-05-07
target/i386: move BSWAP to new decoder
Paolo Bonzini
3
-1
/
+23
2024-05-07
target/i386: move remaining conditional operations to new decoder
Paolo Bonzini
4
-1
/
+68
2024-05-07
target/i386: merge and enlarge a few ranges for call to disas_insn_new
Paolo Bonzini
1
-3
/
+2
2024-05-07
target/i386: move C0-FF opcodes to new decoder (except for x87)
Paolo Bonzini
4
-11
/
+1188
2024-05-07
target/i386: generalize gen_movl_seg_T0
Paolo Bonzini
2
-10
/
+10
2024-05-07
target/i386: move 60-BF opcodes to new decoder
Paolo Bonzini
4
-2
/
+518
2024-05-07
target/i386: allow instructions with more than one immediate
Paolo Bonzini
3
-7
/
+16
2024-05-07
target/i386: extract gen_far_call/jmp, reordering temporaries
Paolo Bonzini
1
-40
/
+53
2024-05-07
target/i386: move 00-5F opcodes to new decoder
Paolo Bonzini
3
-1
/
+323
2024-05-07
target/i386: reintroduce debugging mechanism
Paolo Bonzini
2
-0
/
+30
2024-05-07
target/i386: cleanup *gen_eob*
Paolo Bonzini
1
-13
/
+12
2024-05-07
target/i386: clarify the "reg" argument of functions returning CCPrepare
Paolo Bonzini
1
-7
/
+8
2024-05-07
target/i386: do not use s->T0 and s->T1 as scratch registers for CCPrepare
Paolo Bonzini
1
-7
/
+10
2024-05-07
target/i386: extend cc_* when using them to compute flags
Paolo Bonzini
1
-26
/
+18
2024-05-07
target/i386: pull cc_op update to callers of gen_jmp_rel{,_csize}
Paolo Bonzini
1
-3
/
+5
2024-05-07
target/i386: cleanup cc_op changes for REP/REPZ/REPNZ
Paolo Bonzini
1
-4
/
+10
2024-05-07
target/i386: cc_op is not dynamic in gen_jcc1
Paolo Bonzini
1
-2
/
+2
[next]