| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-02-11 | target/hppa: Allow read-access to PSW with rsm 0,reg instruction | Helge Deller | 1 | -1/+7 |
| 2024-02-11 | target/hppa: Add "diag 0x101" for console output support | Helge Deller | 1 | -0/+6 |
| 2024-01-29 | target: Use vaddr in gen_intermediate_code | Anton Johansson | 1 | -1/+1 |
| 2023-11-17 | target/hppa: Fix 64-bit SHRPD instruction | Helge Deller | 1 | -2/+2 |
| 2023-11-13 | target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX | Richard Henderson | 1 | -3/+3 |
| 2023-11-13 | target/hppa: Introduce MMU_IDX_MMU_DISABLED | Richard Henderson | 1 | -9/+11 |
| 2023-11-13 | target/hppa: Use only low 2 immediate bits for PROBEI | Richard Henderson | 1 | -1/+1 |
| 2023-11-12 | target/hppa: Mask reserved PSW bits in expand_sm_imm | Helge Deller | 1 | -5/+8 |
| 2023-11-06 | target/hppa: Add unwind_breg to CPUHPPAState | Richard Henderson | 1 | -1/+12 |
| 2023-11-06 | target/hppa: Clear upper bits in mtctl for pa1.x | Helge Deller | 1 | -1/+7 |
| 2023-11-06 | target/hppa: Add pa2.0 cpu local tlb flushes | Helge Deller | 1 | -5/+43 |
| 2023-11-06 | target/hppa: Implement pa2.0 data prefetch instructions | Richard Henderson | 1 | -1/+9 |
| 2023-11-06 | target/hppa: Return zero for r0 from load_gpr | Richard Henderson | 1 | -3/+1 |
| 2023-11-06 | target/hppa: Precompute zero into DisasContext | Richard Henderson | 1 | -16/+18 |
| 2023-11-06 | target/hppa: Implement PERMH | Richard Henderson | 1 | -0/+29 |
| 2023-11-06 | target/hppa: Implement MIXH, MIXW | Richard Henderson | 1 | -0/+55 |
| 2023-11-06 | target/hppa: Implement HSHLADD, HSHRADD | Richard Henderson | 1 | -0/+32 |
| 2023-11-06 | target/hppa: Implement HSHL, HSHR | Richard Henderson | 1 | -0/+35 |
| 2023-11-06 | target/hppa: Implement HAVG | Richard Henderson | 1 | -0/+5 |
| 2023-11-06 | target/hppa: Implement HSUB | Richard Henderson | 1 | -0/+15 |
| 2023-11-06 | target/hppa: Implement HADD | Richard Henderson | 1 | -0/+37 |
| 2023-11-06 | target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 | Richard Henderson | 1 | -4/+4 |
| 2023-11-06 | target/hppa: Use tcg_temp_new_i64 not tcg_temp_new | Richard Henderson | 1 | -80/+82 |
| 2023-11-06 | target/hppa: Remove remaining TARGET_REGISTER_BITS redirections | Richard Henderson | 1 | -33/+13 |
| 2023-11-06 | target/hppa: Remove most of the TARGET_REGISTER_BITS redirections | Richard Henderson | 1 | -505/+407 |
| 2023-11-06 | target/hppa: Remove TARGET_REGISTER_BITS | Richard Henderson | 1 | -148/+38 |
| 2023-11-06 | target/hppa: Implement IDTLBT, IITLBT | Richard Henderson | 1 | -6/+36 |
| 2023-11-06 | target/hppa: Implement STDBY | Richard Henderson | 1 | -0/+34 |
| 2023-11-06 | target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM | Richard Henderson | 1 | -0/+6 |
| 2023-11-06 | target/hppa: Implement SHRPD | Richard Henderson | 1 | -30/+69 |
| 2023-11-06 | target/hppa: Implement EXTRD | Richard Henderson | 1 | -11/+31 |
| 2023-11-06 | target/hppa: Implement DEPD, DEPDI | Richard Henderson | 1 | -26/+54 |
| 2023-11-06 | target/hppa: Implement LDD, LDCD, LDDA, STD, STDA | Richard Henderson | 1 | -0/+4 |
| 2023-11-06 | target/hppa: Decode ADDB double-word | Richard Henderson | 1 | -0/+11 |
| 2023-11-06 | target/hppa: Decode CMPIB double-word | Richard Henderson | 1 | -1/+10 |
| 2023-11-06 | target/hppa: Decode d for cmpb instructions | Richard Henderson | 1 | -4/+8 |
| 2023-11-06 | target/hppa: Decode d for bb instructions | Richard Henderson | 1 | -4/+2 |
| 2023-11-06 | target/hppa: Decode d for sub instructions | Richard Henderson | 1 | -11/+11 |
| 2023-11-06 | target/hppa: Decode d for add instructions | Richard Henderson | 1 | -10/+11 |
| 2023-11-06 | target/hppa: Decode d for cmpclr instructions | Richard Henderson | 1 | -6/+5 |
| 2023-11-06 | target/hppa: Decode d for unit instructions | Richard Henderson | 1 | -13/+12 |
| 2023-11-06 | target/hppa: Decode d for logical instructions | Richard Henderson | 1 | -8/+7 |
| 2023-11-06 | target/hppa: Remove TARGET_HPPA64 | Richard Henderson | 1 | -2/+0 |
| 2023-11-06 | target/hppa: Pass d to do_unit_cond | Richard Henderson | 1 | -9/+11 |
| 2023-11-06 | target/hppa: Pass d to do_sed_cond | Richard Henderson | 1 | -11/+13 |
| 2023-11-06 | target/hppa: Pass d to do_log_cond | Richard Henderson | 1 | -10/+38 |
| 2023-11-06 | target/hppa: Pass d to do_sub_cond | Richard Henderson | 1 | -26/+47 |
| 2023-11-06 | target/hppa: Pass d to do_cond | Richard Henderson | 1 | -28/+54 |
| 2023-11-06 | target/hppa: sar register allows only 5 bits on 32-bit CPU | Helge Deller | 1 | -2/+2 |
| 2023-11-06 | target/hppa: Mask inputs in copy_iaoq_entry | Richard Henderson | 1 | -2/+14 |
