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2024-05-15target/hppa: Adjust priv for B,GATE at runtimeRichard Henderson1-7/+27
Do not compile in the priv change based on the first translation; look up the PTE at execution time. This is required for CF_PCREL, where a page may be mapped multiple times with different attributes. Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-15target/hppa: Drop tlb_entry return from hppa_get_physical_addressRichard Henderson1-15/+4
The return-by-reference is never used. Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-15target/hppa: Implement PSW_XRichard Henderson1-17/+25
Use PAGE_WRITE_INV to temporarily enable write permission on for a given page, driven by PSW_X being set. Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-06exec/cpu: Extract page-protection definitions to page-protection.hPhilippe Mathieu-Daudé1-0/+1
Extract page-protection definitions from "exec/cpu-all.h" to "exec/page-protection.h". The list of files requiring the new header was generated using: $ git grep -wE \ 'PAGE_(READ|WRITE|EXEC|RWX|VALID|ANON|RESERVED|TARGET_.|PASSTHROUGH)' Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240427155714.53669-3-philmd@linaro.org>
2024-03-19target/hppa: fix access_id checkSven Schnelle1-17/+61
PA2.0 provides 8 instead of 4 PID registers. Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240319161921.487080-4-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-03-12bulk: Call in place single use cpu_env()Philippe Mathieu-Daudé1-2/+1
Avoid CPUArchState local variable when cpu_env() is used once. Mechanical patch using the following Coccinelle spatch script: @@ type CPUArchState; identifier env; expression cs; @@ { - CPUArchState *env = cpu_env(cs); ... when != env - env + cpu_env(cs) ... when != env } Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240129164514.73104-5-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-03target/hppa: Restore unwind_breg before calculating iorHelge Deller1-1/+2
When calculating the IOR for the exception handlers, the current unwind_breg value is needed on 64-bit hppa machines. Restore that value by calling cpu_restore_state() earlier, which in turn calls hppa_restore_state_to_opc() which restores the unwind_breg for the current instruction. Signed-off-by: Helge Deller <deller@gmx.de> Fixes: 3824e0d643f3 ("target/hppa: Export function hppa_set_ior_and_isr()") Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-11target/hppa: PDC_BTLB_INFO uses 32-bit intsHelge Deller1-1/+1
The BTLB helper function stores the BTLB info (four 32-bit ints) into the memory of the guest. They are only available when emulating a 32-bit CPU in the guest, so use "uint32_t" instead of "target_ulong" here. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-11target/hppa: Implement do_transaction_failed handler for I/O errorsHelge Deller1-0/+19
Add the do_transaction_failed() handler to tigger a HPMC to the CPU in case of I/O transaction errors. This is a preparation commit. We still lack implementation for some registers, so do not yet enable sending HPMCs. Having this hunk here now nevertheless helps for the further development, so that it can easily be enabled later on. Signed-off-by: Helge Deller <deller@gmx.de>
2024-02-03include/exec: Change cpu_mmu_index argument to CPUStateRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-13target/hppa: Export function hppa_set_ior_and_isr()Helge Deller1-11/+12
Move functionality to set IOR and ISR on fault into own function. This will be used by follow-up patches. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-13target/hppa: Avoid accessing %gr0 when raising exceptionHelge Deller1-1/+1
The value of unwind_breg may reference register %r0, but we need to avoid accessing gr0 directly and use the value 0 instead. At runtime I've seen unwind_breg being zero with the Linux kernel when rfi is used to jump to smp_callin(). Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Bruno Haible <bruno@clisp.org>
2024-01-13target/hppa: Fix PDC address translation on PA2.0 with PSW.W=0Helge Deller1-2/+8
Fix the address translation for PDC space on PA2.0 if PSW.W=0. Basically, for any address in the 32-bit PDC range from 0xf0000000 to 0xf1000000 keep the lower 32-bits and just set the upper 32-bits to 0xfffffff0. This mapping fixes the emulated power button in PDC space for 32- and 64-bit machines and is how the physical C3700 machine seems to map PDC. Figures H-10 and H-11 in the parisc2.0 spec [1] show that the 32-bit region will be mapped somewhere into a higher and bigger 64-bit PDC space. The start and end of this 64-bit space is defined by the physical address bits. But the figures don't specifiy where exactly the mapping will start inside that region. Tests on a real HP C3700 regarding the address of the power button indicate, that the lower 32-bits will stay the same though. [1] https://parisc.wiki.kernel.org/images-parisc/7/73/Parisc2.0.pdf Signed-off-by: Helge Deller <deller@gmx.de> Tested-by: Bruno Haible <bruno@clisp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40Richard Henderson1-17/+33
This is the value that is supported by both PA-8500 and Astro. If we support a larger address space than expected, we trip up software that did not fill in all of the page table bits, expecting them to be ignored. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDXRichard Henderson1-20/+21
Align the language with pa2.0, separating absolute and physical. The translation from absolute to physical depends on PSW.W, and we prefer not to flush between changes, therefore use 2 mmu_idx. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Introduce MMU_IDX_MMU_DISABLEDRichard Henderson1-2/+2
Reduce the number of direct checks against MMU_PHYS_IDX. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Fix possible overflow in TLB size calculationHelge Deller1-2/+2
Coverty found that the shift of TARGET_PAGE_SIZE (32-bit type) might overflow. Fix it by casting TARGET_PAGE_SIZE to a 64-bit type before doing the shift (CID 1523902 and CID 1523908). Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <ZU6F/H8CZr3q4pP/@p100> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Create raise_exception_with_iorRichard Henderson1-13/+51
Handle pa2.0 logic for filling in ISR+IOR. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Avoid async_safe_run_on_cpu on uniprocessor systemRichard Henderson1-1/+7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add pa2.0 cpu local tlb flushesHelge Deller1-4/+22
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe". PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b]. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_REGISTER_BITSRichard Henderson1-8/+8
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement IDTLBT, IITLBTRichard Henderson1-5/+56
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Handle absolute addresses for pa2.0Richard Henderson1-2/+41
With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Make HPPA_BTLB_ENTRIES variableRichard Henderson1-18/+22
Depend on hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Populate an interval tree with valid tlb entriesRichard Henderson1-65/+96
Complete the data structure conversion started earlier. This reduces the perf overhead of hppa_get_physical_address from ~5% to ~0.25%. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Split out hppa_flush_tlb_rangeRichard Henderson1-15/+24
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Always report one page to tlb_set_pageRichard Henderson1-2/+9
No need to trigger the large_page_mask code unnecessarily. Drop the now unused HPPATLBEntry.page_size field. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use IntervalTreeNode in HPPATLBEntryRichard Henderson1-14/+17
Replace the va_b and va_b fields with the interval tree node. The actual interval tree is not yet used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Rename hppa_tlb_entry to HPPATLBEntryRichard Henderson1-15/+15
Rename to CamelCase per coding style. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Include PSW_P in tb flags and mmu indexRichard Henderson1-4/+2
Use a separate mmu index for PSW_P enabled vs disabled. This means we can elide the tlb flush in cpu_hppa_put_psw when PSW_P changes. This turns out to be the majority of all tlb flushes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson1-1/+1
Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-19target/hppa: Wire up diag instruction to support BTLBHelge Deller1-0/+92
Wire up the hppa diag instruction to support Block-TLBs when called with the 0x100 value. The diag_btlb() helper function does all necessary steps to emulate the PDC BTLB firmware function, which includes providing BTLB info, adding a new BTLB, deleting a BTLB and removing all BTLBs. Signed-off-by: Helge Deller <deller@gmx.de>
2023-09-15target/hppa: Add BTLB support to hppa TLB functionsHelge Deller1-27/+60
Change the TLB code to store the Block-TLBs at the beginning of the TLB table. New 4k TLB entries which are added later shall not overwrite any of the BTLB entries. Make sure that when the TLB is cleared by the OS via the ptlbe instruction, the Block-TLBs will not be dropped. Signed-off-by: Helge Deller <deller@gmx.de>
2023-08-25target/hppa: Use privilege helper in hppa_get_physical_address()Helge Deller1-4/+5
Convert hppa_get_physical_address() to use the privilege helper macro. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-08-25target/hppa: Do not use hardcoded value for tlb_flush_*()Helge Deller1-4/+3
Avoid using hardcoded values when calling the tlb_flush*() functions. Instead, define and use HPPA_MMU_FLUSH_MASK (keeping the current behavior, which doesn't flush the physical address MMU). Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé1-0/+1
Many files use "qemu/log.h" declarations but neglect to include it (they inherit it via "exec/exec-all.h"). "exec/exec-all.h" is a core component and shouldn't be used that way. Move the "qemu/log.h" inclusion locally to each unit requiring it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220207082756.82600-10-f4bug@amsat.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-11-02target/hppa: Make hppa_cpu_tlb_fill sysemu onlyRichard Henderson1-15/+0
The fallback code in cpu_loop_exit_sigsegv is sufficient for hppa linux-user. Remove the code from cpu_loop that raised SIGSEGV. This makes all of the code in mem_helper.c sysemu only, so remove the ifdefs and move the file to hppa_softmmu_ss. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-11-15overall/alpha tcg cpus|hppa: Fix Lesser GPL version numberChetan Pant1-1/+1
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023123353.19796-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster1-1/+1
Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190709152053.16670-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [Rebased onto merge commit 95a9457fd44; missed instances of qom/cpu.h in comments replaced]
2019-06-10target/hppa: Use env_cpu, env_archcpuRichard Henderson1-6/+4
Cleanup in the boilerplate that each target must define. Replace hppa_env_get_cpu with env_archcpu. The combination CPU(hppa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-6/+0
We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10target/hppa: Convert to CPUClass::tlb_fillRichard Henderson1-5/+17
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-04-29target/hppa: Always return EXCP_DMAR for protection id trapNick Hudson1-2/+1
The EXCP_DMP trap is considered legacy. "In PA-RISC 1.1 (Second Edition) and later revisions, processors must use traps 26, 27,and 28 which provide equivalent functionality" Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20190423063621.8203-3-nick.hudson@gmx.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12target/hppa: add TLB protection id checkSven Schnelle1-1/+27
Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-10-svens@stackframe.org> [rth: Add required tlb flushing when prot id registers change.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12target/hppa: allow multiple itlbp without itlbaSven Schnelle1-1/+1
The ODE software calls itlbp on existing TLB entries without calling itlba first, so this seems to be valid. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-9-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12target/hppa: add TLB trace eventsSven Schnelle1-2/+19
To ease TLB debugging add a few trace events, which are disabled by default so that there's no performance impact. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-5-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12target/hppa: report ITLB_EXCP_MISS for ITLB missesSven Schnelle1-3/+1
Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-4-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12target/hppa: fix TLB handling for page 0Sven Schnelle1-5/+7
Assume the following sequence: pitlbe r0(sr0,r0) iitlba r4,(sr0,r0) ldil L%3000000,r5 iitlbp r5,(sr0,r0) This will purge the whole TLB and add an entry for page 0. However the current TLB implementation in helper_iitlba() will store to the last empty TLB entry, while helper_iitlbp() will write to the first empty entry. That is because an empty entry will match address 0 in helper_iitlba() Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190311191602.25796-3-svens@stackframe.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-16target/hppa: Raise exception 26 on emulated hardwareHelge Deller1-1/+2
On PCXS chips (PA7000, pa 1.1a), trap #18 is raised on memory faults, while all later chips (>= PA7100) generate either trap #26, #27 or #28 (depending on the fault type). Since the current qemu emulation emulates a B160L machine (with a PA7300LC PCX-L2 chip, we should raise trap #26 (EXCP_DMAR) instead of #18 (EXCP_DMP) on access faults by the Linux kernel to page zero. With the patch we now get the correct output (I tested against real hardware): Kernel Fault: Code=26 (Data memory access rights trap) instead of: Kernel Fault: Code=18 (Data memory protection/unaligned access trap) Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20181007205153.GA30270@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Only use EXCP_DTLB_MISSRichard Henderson1-1/+3
Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-07-21 04:28:45 +0000