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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-11-01 15:17:04 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 18:49:33 -0800 |
| commit | bb67ec32a0bb90a4d392a778f97f1e86ed75f0a9 (patch) | |
| tree | b32aa34d716d3492f3ae892a8f0bdf522ba60b7e /target/hppa/mem_helper.c | |
| parent | 3e01f1147a16ca566694b97eafc941d62fa1e8d8 (diff) | |
| download | qemu-bb67ec32a0bb90a4d392a778f97f1e86ed75f0a9.zip qemu-bb67ec32a0bb90a4d392a778f97f1e86ed75f0a9.tar.gz qemu-bb67ec32a0bb90a4d392a778f97f1e86ed75f0a9.tar.bz2 | |
target/hppa: Include PSW_P in tb flags and mmu index
Use a separate mmu index for PSW_P enabled vs disabled.
This means we can elide the tlb flush in cpu_hppa_put_psw
when PSW_P changes. This turns out to be the majority
of all tlb flushes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/mem_helper.c')
| -rw-r--r-- | target/hppa/mem_helper.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 350485f..7290322 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -144,7 +144,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, } /* access_id == 0 means public page and no check is performed */ - if ((env->psw & PSW_P) && ent->access_id) { + if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { /* If bits [31:1] match, and bit 0 is set, suppress write. */ int match = ent->access_id * 2 + 1; @@ -373,9 +373,7 @@ void HELPER(ptlbe)(CPUHPPAState *env) void cpu_hppa_change_prot_id(CPUHPPAState *env) { - if (env->psw & PSW_P) { - tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); - } + tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_P_MASK); } void HELPER(change_prot_id)(CPUHPPAState *env) |