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AgeCommit message (Expand)AuthorFilesLines
2023-07-08target/avr: Fix handling of interrupts above 33.Lucas Dietrich1-2/+2
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé1-3/+3
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-1/+0
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+5
2023-06-05target/*: Add missing includes of tcg/debug-assert.hRichard Henderson1-0/+1
2023-06-05target/avr: Add missing includes of qemu/error-report.hRichard Henderson1-0/+1
2023-05-05target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*Richard Henderson1-8/+8
2023-03-13target/avr: Avoid use of tcg_const_i32 throughoutRichard Henderson1-15/+15
2023-03-13target/avr: Avoid use of tcg_const_i32 in SBIC, SBISRichard Henderson1-8/+10
2023-03-13target/avr: Remove `NB_MMU_MODES` defineAnton Johansson1-1/+0
2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée1-1/+1
2023-03-05target/avr: Drop tcg_temp_freeRichard Henderson1-228/+0
2023-03-05target/avr: Drop R from trans_COMRichard Henderson1-4/+0
2023-03-05target/avr: Drop DisasContext.free_skip_var0Richard Henderson1-19/+0
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
2023-03-01target/avr: Replace `tb_pc()` with `tb->pc`Anton Johansson1-1/+2
2022-12-16target/avr: Convert to 3-phase resetPeter Maydell2-6/+11
2022-12-14cleanup: Tweak and re-run return_directly.cocciMarkus Armbruster1-3/+1
2022-10-26target/avr: Convert to tcg_ops restore_state_to_opcRichard Henderson2-6/+11
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson1-1/+1
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson1-0/+8
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+3
2022-09-01target/avr: Disable interrupts when env->skip setRichard Henderson2-4/+31
2022-09-01target/avr: Only execute one interrupt at a timeRichard Henderson1-6/+3
2022-09-01target/avr: Call avr_cpu_do_interrupt directlyRichard Henderson1-3/+2
2022-09-01target/avr: Support probe argument to tlb_fillRichard Henderson1-17/+29
2022-06-20target/avr: Drop avr_cpu_memory_rw_debug()Bin Meng3-9/+0
2022-05-11Clean up decorations and whitespace around header guardsMarkus Armbruster1-1/+1
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster1-3/+3
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2-6/+3
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-5/+2
2022-02-22Merge remote-tracking branch 'remotes/lvivier-gitlab/tags/trivial-branch-for-...Peter Maydell1-1/+0
2022-02-21target/avr: Correct AVRCPUClass docstringPhilippe Mathieu-Daudé1-1/+0
2022-02-21exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé1-0/+1
2021-10-15target/avr: Drop checks for singlestep_enabledRichard Henderson1-15/+4
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-2/+0
2021-09-16Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.2-pul...Peter Maydell1-5/+3
2021-09-16target/avr: Fix compiler errors (-Werror=enum-conversion)Stefan Weil1-5/+3
2021-09-14target/avr: Remove pointless use of CONFIG_USER_ONLY definitionPhilippe Mathieu-Daudé1-3/+0
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-18/+0
2021-07-21target/avr: Implement gdb_adjust_breakpointRichard Henderson4-14/+15
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2-7/+10
2021-07-09target/avr: Mark some helpers noreturnRichard Henderson1-4/+4
2021-07-09target/avr: Use translator_use_goto_tbRichard Henderson1-3/+6
2021-07-09meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé1-0/+2
2021-06-29target/avr: Convert to TranslatorOpsRichard Henderson1-104/+126
2021-06-29target/avr: Change ctx to DisasContext* in gen_intermediate_codeRichard Henderson1-41/+43