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author | Richard Henderson <richard.henderson@linaro.org> | 2023-02-24 18:05:08 -1000 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2023-03-05 13:44:07 -0800 |
commit | c1110449334c05cb7fc24ecca76de5620d1f596f (patch) | |
tree | 1d1301f4237c9c1058fc0c4bf66c1973abe9d238 /target/avr | |
parent | 9cf1fe2cc055f78343710166a322ad88d57b31ad (diff) | |
download | qemu-c1110449334c05cb7fc24ecca76de5620d1f596f.zip qemu-c1110449334c05cb7fc24ecca76de5620d1f596f.tar.gz qemu-c1110449334c05cb7fc24ecca76de5620d1f596f.tar.bz2 |
target/avr: Drop DisasContext.free_skip_var0
Translators are no longer required to free tcg temporaries,
therefore there's no need to record for later freeing.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/avr')
-rw-r--r-- | target/avr/translate.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/target/avr/translate.c b/target/avr/translate.c index e40d8e9..e7f0e2b 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -107,11 +107,6 @@ struct DisasContext { * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); * } * - * if (free_skip_var0) { - * tcg_temp_free(skip_var0); - * free_skip_var0 = false; - * } - * * translate(ctx); * * if (skip_label) { @@ -121,7 +116,6 @@ struct DisasContext { TCGv skip_var0; TCGv skip_var1; TCGCond skip_cond; - bool free_skip_var0; }; void avr_cpu_tcg_init(void) @@ -1375,7 +1369,6 @@ static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a) ctx->skip_cond = TCG_COND_EQ; ctx->skip_var0 = tcg_temp_new(); - ctx->free_skip_var0 = true; tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); return true; @@ -1391,7 +1384,6 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) ctx->skip_cond = TCG_COND_NE; ctx->skip_var0 = tcg_temp_new(); - ctx->free_skip_var0 = true; tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); return true; @@ -1410,7 +1402,6 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond = TCG_COND_EQ; ctx->skip_var0 = temp; - ctx->free_skip_var0 = true; return true; } @@ -1428,7 +1419,6 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond = TCG_COND_NE; ctx->skip_var0 = temp; - ctx->free_skip_var0 = true; return true; } @@ -2886,10 +2876,6 @@ static bool canonicalize_skip(DisasContext *ctx) ctx->skip_cond = TCG_COND_NE; break; } - if (ctx->free_skip_var0) { - tcg_temp_free(ctx->skip_var0); - ctx->free_skip_var0 = false; - } ctx->skip_var0 = cpu_skip; return true; } @@ -2944,7 +2930,6 @@ static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) * This ensures that cpu_skip is non-zero after the label * if and only if the skipped insn itself sets a skip. */ - ctx->free_skip_var0 = true; ctx->skip_var0 = tcg_temp_new(); tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); tcg_gen_movi_tl(cpu_skip, 0); @@ -2956,10 +2941,6 @@ static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) ctx->skip_var1, skip_label); ctx->skip_var1 = NULL; } - if (ctx->free_skip_var0) { - tcg_temp_free(ctx->skip_var0); - ctx->free_skip_var0 = false; - } ctx->skip_cond = TCG_COND_NEVER; ctx->skip_var0 = NULL; } |