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Author
Files
Lines
2021-07-18
target/arm: Remove duplicate 'plus1' function from Neon and SVE decode
Peter Maydell
5
-14
/
+4
2021-07-18
target/arm: Fix offsets for TTBCR
Richard Henderson
1
-4
/
+7
2021-07-12
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...
Peter Maydell
3
-36
/
+8
2021-07-11
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...
Peter Maydell
1
-0
/
+6
2021-07-09
target/arm: Use translator_use_goto_tb for aarch32
Richard Henderson
1
-11
/
+1
2021-07-09
target/arm: Use translator_use_goto_tb for aarch64
Richard Henderson
1
-20
/
+5
2021-07-09
target/arm: Use DISAS_TOO_MANY for ISB and SB
Richard Henderson
1
-2
/
+2
2021-07-09
tcg: Avoid including 'trace-tcg.h' in target translate.c
Philippe Mathieu-Daudé
3
-3
/
+0
2021-07-09
meson: Introduce target-specific Kconfig
Philippe Mathieu-Daudé
1
-0
/
+6
2021-07-09
target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
hnick@vmware.com
1
-3
/
+13
2021-07-02
target/arm: Implement MVE shifts by register
Peter Maydell
5
-4
/
+57
2021-07-02
target/arm: Implement MVE shifts by immediate
Peter Maydell
5
-10
/
+105
2021-07-02
target/arm: Implement MVE long shifts by register
Peter Maydell
5
-3
/
+182
2021-07-02
target/arm: Implement MVE long shifts by immediate
Peter Maydell
5
-0
/
+132
2021-07-02
target/arm: Implement MVE VADDLV
Peter Maydell
4
-1
/
+90
2021-07-02
target/arm: Implement MVE VSHLC
Peter Maydell
4
-0
/
+72
2021-07-02
target/arm: Implement MVE saturating narrowing shifts
Peter Maydell
4
-0
/
+174
2021-07-02
target/arm: Implement MVE VSHRN, VRSHRN
Peter Maydell
4
-0
/
+76
2021-07-02
target/arm: Implement MVE VSRI, VSLI
Peter Maydell
4
-0
/
+62
2021-07-02
target/arm: Implement MVE VSHLL
Peter Maydell
4
-4
/
+105
2021-07-02
target/arm: Implement MVE vector shift right by immediate insns
Peter Maydell
6
-18
/
+72
2021-07-02
target/arm: Implement MVE vector shift left by immediate insns
Peter Maydell
4
-0
/
+147
2021-07-02
target/arm: Implement MVE logical immediate insns
Peter Maydell
4
-0
/
+95
2021-07-02
target/arm: Use dup_const() instead of bitfield_replicate()
Peter Maydell
1
-1
/
+1
2021-07-02
target/arm: Use asimd_imm_const for A64 decode
Peter Maydell
3
-82
/
+24
2021-07-02
target/arm: Make asimd_imm_const() public
Peter Maydell
3
-63
/
+73
2021-07-02
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
Peter Maydell
1
-17
/
+21
2021-07-02
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
Peter Maydell
1
-8
/
+9
2021-07-02
target/arm: Check NaN mode before silencing NaN
Joe Komlodi
2
-9
/
+27
2021-06-29
target/arm: Improve REVSH
Richard Henderson
1
-3
/
+1
2021-06-29
target/arm: Improve vector REV
Richard Henderson
1
-4
/
+2
2021-06-29
target/arm: Improve REV32
Richard Henderson
1
-13
/
+4
2021-06-29
tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64
Richard Henderson
2
-6
/
+8
2021-06-24
target/arm: Implement MTE3
Peter Collingbourne
2
-32
/
+52
2021-06-24
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
Peter Maydell
3
-8
/
+75
2021-06-24
target/arm: Implement MVE VADDV
Peter Maydell
4
-0
/
+76
2021-06-24
target/arm: Implement MVE VHCADD
Peter Maydell
4
-3
/
+19
2021-06-24
target/arm: Implement MVE VCADD
Peter Maydell
4
-2
/
+51
2021-06-24
target/arm: Implement MVE VADC, VSBC
Peter Maydell
4
-0
/
+99
2021-06-24
target/arm: Implement MVE VRHADD
Peter Maydell
4
-0
/
+19
2021-06-24
target/arm: Implement MVE VQDMULL (vector)
Peter Maydell
4
-0
/
+70
2021-06-24
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
Peter Maydell
4
-0
/
+69
2021-06-24
target/arm: Implement MVE VQDMLADH and VQRDMLADH
Peter Maydell
4
-0
/
+114
2021-06-24
target/arm: Implement MVE VRSHL
Peter Maydell
4
-0
/
+17
2021-06-24
target/arm: Implement MVE VSHL insn
Peter Maydell
4
-0
/
+19
2021-06-24
target/arm: Implement MVE VQRSHL
Peter Maydell
4
-0
/
+19
2021-06-24
target/arm: Implement MVE VQSHL (vector)
Peter Maydell
4
-0
/
+56
2021-06-24
target/arm: Implement MVE VQADD, VQSUB (vector)
Peter Maydell
4
-0
/
+39
2021-06-24
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
Peter Maydell
4
-0
/
+40
2021-06-24
target/arm: Implement MVE VQDMULL scalar
Peter Maydell
4
-4
/
+119
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