| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2019-10-15 | target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension | Peter Maydell | 1 | -2/+17 |
| 2019-10-15 | target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension | Peter Maydell | 1 | -5/+14 |
| 2019-10-15 | target/arm/arm-semi: Implement support for semihosting feature detection | Peter Maydell | 1 | -1/+108 |
| 2019-10-15 | target/arm/arm-semi: Factor out implementation of SYS_FLEN | Peter Maydell | 1 | -10/+22 |
| 2019-10-15 | target/arm/arm-semi: Factor out implementation of SYS_SEEK | Peter Maydell | 1 | -9/+22 |
| 2019-10-15 | target/arm/arm-semi: Factor out implementation of SYS_ISTTY | Peter Maydell | 1 | -5/+15 |
| 2019-10-15 | target/arm/arm-semi: Factor out implementation of SYS_READ | Peter Maydell | 1 | -20/+35 |
| 2019-10-15 | target/arm/arm-semi: Factor out implementation of SYS_WRITE | Peter Maydell | 1 | -18/+33 |
| 2019-10-15 | target/arm/arm-semi: Factor out implementation of SYS_CLOSE | Peter Maydell | 1 | -7/+37 |
| 2019-10-15 | target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions | Peter Maydell | 1 | -21/+6 |
| 2019-10-15 | target/arm/arm-semi: Restrict use of TaskState* | Peter Maydell | 1 | -48/+63 |
| 2019-10-15 | target/arm/arm-semi: Make semihosting code hand out its own file descriptors | Peter Maydell | 1 | -14/+214 |
| 2019-10-15 | target/arm/arm-semi: Correct comment about gdb syscall races | Peter Maydell | 1 | -4/+15 |
| 2019-10-15 | target/arm/arm-semi: Always set some kind of errno for failed calls | Peter Maydell | 1 | -18/+27 |
| 2019-10-15 | target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno() | Peter Maydell | 1 | -4/+5 |
| 2019-10-15 | ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256 | Eric Auger | 1 | -1/+9 |
| 2019-10-15 | intc/arm_gic: Support IRQ injection for more than 256 vpus | Eric Auger | 3 | -6/+17 |
| 2019-09-27 | target/arm: remove run time semihosting checks | Alex Bennée | 1 | -74/+22 |
| 2019-09-27 | target/arm: handle A-profile semihosting at translate time | Alex Bennée | 1 | -4/+15 |
| 2019-09-27 | target/arm: handle M-profile semihosting at translate time | Alex Bennée | 2 | -13/+16 |
| 2019-09-27 | target/arm: fix CBAR register for AArch64 CPUs | Luc Michel | 1 | -3/+16 |
| 2019-09-05 | target/arm: Inline gen_bx_im into callers | Richard Henderson | 1 | -19/+7 |
| 2019-09-05 | target/arm: Clean up disas_thumb_insn | Richard Henderson | 1 | -25/+2 |
| 2019-09-05 | target/arm: Convert T16, long branches | Richard Henderson | 2 | -49/+43 |
| 2019-09-05 | target/arm: Convert T16, Unconditional branch | Richard Henderson | 2 | -7/+8 |
| 2019-09-05 | target/arm: Convert T16, load (literal) | Richard Henderson | 2 | -40/+6 |
| 2019-09-05 | target/arm: Convert T16, shift immediate | Richard Henderson | 2 | -24/+10 |
| 2019-09-05 | target/arm: Convert T16, Miscellaneous 16-bit instructions | Richard Henderson | 2 | -87/+55 |
| 2019-09-05 | target/arm: Convert T16, Conditional branches, Supervisor call | Richard Henderson | 2 | -23/+15 |
| 2019-09-05 | target/arm: Convert T16, push and pop | Richard Henderson | 2 | -71/+22 |
| 2019-09-05 | target/arm: Split gen_nop_hint | Richard Henderson | 1 | -43/+24 |
| 2019-09-05 | target/arm: Convert T16, nop hints | Richard Henderson | 2 | -2/+18 |
| 2019-09-05 | target/arm: Convert T16, Reverse bytes | Richard Henderson | 2 | -15/+12 |
| 2019-09-05 | target/arm: Convert T16, Change processor state | Richard Henderson | 2 | -46/+50 |
| 2019-09-05 | target/arm: Convert T16, extract | Richard Henderson | 2 | -13/+11 |
| 2019-09-05 | target/arm: Convert T16 adjust sp (immediate) | Richard Henderson | 2 | -13/+11 |
| 2019-09-05 | target/arm: Convert T16 add, compare, move (two high registers) | Richard Henderson | 2 | -47/+12 |
| 2019-09-05 | target/arm: Convert T16 branch and exchange | Richard Henderson | 2 | -41/+39 |
| 2019-09-05 | target/arm: Convert T16 one low register and immediate | Richard Henderson | 2 | -42/+13 |
| 2019-09-05 | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson | 2 | -24/+18 |
| 2019-09-05 | target/arm: Convert T16 load/store multiple | Richard Henderson | 2 | -39/+17 |
| 2019-09-05 | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson | 2 | -11/+8 |
| 2019-09-05 | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson | 2 | -89/+38 |
| 2019-09-05 | target/arm: Convert T16 load/store (register offset) | Richard Henderson | 2 | -49/+17 |
| 2019-09-05 | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson | 2 | -145/+43 |
| 2019-09-05 | target/arm: Add skeleton for T16 decodetree | Richard Henderson | 3 | -0/+32 |
| 2019-09-05 | target/arm: Simplify disas_arm_insn | Richard Henderson | 1 | -53/+16 |
| 2019-09-05 | target/arm: Simplify disas_thumb2_insn | Richard Henderson | 1 | -76/+3 |
| 2019-09-05 | target/arm: Convert TT | Richard Henderson | 2 | -61/+34 |
| 2019-09-05 | target/arm: Convert SG | Richard Henderson | 2 | -23/+33 |
