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path: root/target/arm/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2018-11-13target/arm: Track the state of our irq lines from the GIC explicitlyPeter Maydell1-0/+3
2018-11-13arm: fix aa64_generate_debug_exceptions to work with EL2Alex Bennée1-15/+24
2018-11-13arm: use symbolic MDCR_TDE in arm_debug_target_elAlex Bennée1-1/+1
2018-11-02target/arm: Conditionalize some asserts on aarch32 supportRichard Henderson1-0/+5
2018-10-24target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 testRichard Henderson1-1/+16
2018-10-24target/arm: Convert sve from feature bit to aa64pfr0 testRichard Henderson1-1/+15
2018-10-24target/arm: Convert jazelle from feature bit to isar1 testRichard Henderson1-1/+5
2018-10-24target/arm: Convert division from feature bits to isar0 testsRichard Henderson1-2/+10
2018-10-24target/arm: Convert v8 extensions from feature bits to isar testsRichard Henderson1-12/+119
2018-10-24target/arm: Move some system registers into a substructureRichard Henderson1-14/+18
2018-10-24target/arm: Add support for VCPU event statesDongjiu Geng1-0/+7
2018-10-16target/arm: Define fields of ISAR registersRichard Henderson1-0/+88
2018-10-16target/arm: Fix aarch64_sve_change_el wrt EL0Richard Henderson1-2/+5
2018-10-08target/arm: Define new EXCP type for v8M stack overflowsPeter Maydell1-0/+2
2018-10-08target/arm: Define new TBFLAG for v8M stack checkingPeter Maydell1-0/+7
2018-10-08target/arm: Adjust aarch64_cpu_dump_state for system mode SVERichard Henderson1-0/+4
2018-10-08target/arm: Handle SVE vector length changes in system modeRichard Henderson1-0/+4
2018-08-24target/arm: Remove a handful of stray tabsPeter Maydell1-8/+8
2018-08-16target/arm: Adjust FPCR_MASK for FZ16Richard Henderson1-1/+1
2018-08-16target/arm: Add sve-max-vq cpu property to -cpu maxRichard Henderson1-0/+3
2018-08-14target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}Peter Maydell1-6/+58
2018-08-14target/arm: Mask virtual interrupts if HCR_EL2.TGE is setPeter Maydell1-2/+4
2018-06-29target/arm: Add ID_ISAR6Richard Henderson1-0/+1
2018-06-29target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization ExtensionsAaron Lindsay1-0/+1
2018-06-29target/arm: Implement ARMv8.2-DotProdRichard Henderson1-0/+1
2018-06-22target/arm: Introduce ARM_FEATURE_M_MAINJulia Suvorova1-0/+1
2018-05-18target/arm: Implement SVE Predicate Misc GroupRichard Henderson1-0/+4
2018-05-18target/arm: Implement SVE Predicate Logical Operations GroupRichard Henderson1-1/+3
2018-05-18target/arm: Add the XML dynamic generationAbdallah Bouassida1-0/+26
2018-05-18target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo typeAbdallah Bouassida1-1/+2
2018-05-10target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decodeRichard Henderson1-0/+1
2018-04-26target/arm: Make PMOVSCLR and PMUSERENR 64 bits wideAaron Lindsay1-2/+2
2018-04-26target/arm: Add pre-EL change hooksAaron Lindsay1-3/+19
2018-04-26target/arm: Support multiple EL change hooksAaron Lindsay1-10/+10
2018-04-26target/arm: Fetch GICv3 state directly from CPUARMStateAaron Lindsay1-10/+0
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-2/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-03-09target/arm: Query host CPU features on-demand at instance initPeter Maydell1-0/+5
2018-03-09linux-user: Implement aarch64 PR_SVE_SET/GET_VLRichard Henderson1-0/+1
2018-03-09target/arm: Add a core count propertyAlistair Francis1-0/+5
2018-03-02target/arm: Add ARM_FEATURE_V8_FCMARichard Henderson1-0/+1
2018-03-02target/arm: Add ARM_FEATURE_V8_RDMRichard Henderson1-0/+1
2018-03-02target/arm: Define init-svtor property for the reset secure VTOR valuePeter Maydell1-0/+3
2018-03-02target/arm: Define an IDAU interfacePeter Maydell1-0/+3
2018-03-01target/arm/cpu.h: add additional float_status flagsAlex Bennée1-7/+25
2018-03-01target/arm/cpu.h: update comment for half-precision valuesAlex Bennée1-0/+1
2018-03-01target/arm/cpu64: introduce ARM_V8_FP16 feature bitAlex Bennée1-0/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée1-2/+0
2018-02-15target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell1-0/+2
2018-02-15hw/intc/armv7m_nvic: Implement SCRPeter Maydell1-0/+7
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