index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-xtensa
/
op_helper.c
Age
Commit message (
Expand
)
Author
Files
Lines
2013-06-28
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Andreas Färber
1
-1
/
+3
2013-03-12
cpu: Move halted and interrupt_request fields to CPUState
Andreas Färber
1
-1
/
+4
2012-12-19
misc: move include files to include/qemu/
Paolo Bonzini
1
-1
/
+1
2012-12-19
exec: move include files to include/exec/
Paolo Bonzini
1
-4
/
+4
2012-12-16
exec: refactor cpu_restore_state
Blue Swirl
1
-12
/
+2
2012-12-08
target-xtensa: implement ATOMCTL SR
Max Filippov
1
-0
/
+57
2012-09-22
target-xtensa: implement FP1 group
Max Filippov
1
-0
/
+47
2012-09-22
target-xtensa: implement FP0 conversions
Max Filippov
1
-0
/
+37
2012-09-22
target-xtensa: implement FP0 arithmetic
Max Filippov
1
-0
/
+37
2012-09-22
target-xtensa: add FP registers
Max Filippov
1
-0
/
+13
2012-06-10
target-xtensa: switch to AREG0-free mode
Max Filippov
1
-95
/
+90
2012-06-09
target-xtensa: update autorefill TLB entries conditionally
Max Filippov
1
-2
/
+2
2012-06-09
target-xtensa: extract TLB entry setting method
Max Filippov
1
-4
/
+11
2012-06-09
target-xtensa: flush TLB page for new MMU mapping
Max Filippov
1
-0
/
+1
2012-04-14
target-xtensa: fix tb invalidation for IBREAK and LOOP
Max Filippov
1
-11
/
+18
2012-04-14
Use uintptr_t for various op related functions
Blue Swirl
1
-5
/
+4
2012-04-14
target-xtensa: Move helpers.h to helper.h
Lluís Vilanova
1
-1
/
+1
2012-03-14
target-xtensa: Don't overuse CPUState
Andreas Färber
1
-15
/
+15
2012-02-20
target-xtensa: add DBREAK data breakpoints
Max Filippov
1
-0
/
+62
2012-02-18
target-xtensa: implement instruction breakpoints
Max Filippov
1
-0
/
+38
2011-10-15
target-xtensa: fix guest hang on masked CCOMPARE interrupt
Max Filippov
1
-15
/
+3
2011-10-01
softmmu_header: pass CPUState to tlb_fill
Blue Swirl
1
-2
/
+3
2011-09-10
target-xtensa: implement memory protection options
Max Filippov
1
-6
/
+295
2011-09-10
target-xtensa: implement interrupt option
Max Filippov
1
-0
/
+46
2011-09-10
target-xtensa: implement unaligned exception option
Max Filippov
1
-0
/
+26
2011-09-10
target-xtensa: implement loop option
Max Filippov
1
-0
/
+20
2011-09-10
target-xtensa: implement windowed registers
Max Filippov
1
-0
/
+192
2011-09-10
target-xtensa: implement exceptions
Max Filippov
1
-0
/
+29
2011-09-10
target-xtensa: implement shifts (ST1 and RST1 groups)
Max Filippov
1
-0
/
+14
2011-09-10
target-xtensa: implement disas_xtensa_insn
Max Filippov
1
-0
/
+7
2011-09-10
target-xtensa: add target stubs
Max Filippov
1
-0
/
+52