diff options
author | Andreas Färber <afaerber@suse.de> | 2012-03-14 01:38:23 +0100 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2012-03-14 22:20:25 +0100 |
commit | 97129ac899633325000c4d40b53b1afa0975f541 (patch) | |
tree | ef93ee8cdbce00eb6576069dd5e950182e036543 /target-xtensa/op_helper.c | |
parent | eb23b556aa57aca4c0a822236c4baf96ae2ac216 (diff) | |
download | qemu-97129ac899633325000c4d40b53b1afa0975f541.zip qemu-97129ac899633325000c4d40b53b1afa0975f541.tar.gz qemu-97129ac899633325000c4d40b53b1afa0975f541.tar.bz2 |
target-xtensa: Don't overuse CPUState
Scripted conversion:
sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc]
sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'target-xtensa/op_helper.c')
-rw-r--r-- | target-xtensa/op_helper.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index e184cf6..cdef0db 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -70,10 +70,10 @@ static void do_unaligned_access(target_ulong addr, int is_write, int is_user, } } -void tlb_fill(CPUState *env1, target_ulong vaddr, int is_write, int mmu_idx, +void tlb_fill(CPUXtensaState *env1, target_ulong vaddr, int is_write, int mmu_idx, void *retaddr) { - CPUState *saved_env = env; + CPUXtensaState *saved_env = env; env = env1; { @@ -134,7 +134,7 @@ void HELPER(exception_cause_vaddr)(uint32_t pc, uint32_t cause, uint32_t vaddr) HELPER(exception_cause)(pc, cause); } -void debug_exception_env(CPUState *new_env, uint32_t cause) +void debug_exception_env(CPUXtensaState *new_env, uint32_t cause) { if (xtensa_get_cintlevel(new_env) < new_env->config->debug_level) { env = new_env; @@ -168,7 +168,7 @@ uint32_t HELPER(nsau)(uint32_t v) return v ? clz32(v) : 32; } -static void copy_window_from_phys(CPUState *env, +static void copy_window_from_phys(CPUXtensaState *env, uint32_t window, uint32_t phys, uint32_t n) { assert(phys < env->config->nareg); @@ -184,7 +184,7 @@ static void copy_window_from_phys(CPUState *env, } } -static void copy_phys_from_window(CPUState *env, +static void copy_phys_from_window(CPUXtensaState *env, uint32_t phys, uint32_t window, uint32_t n) { assert(phys < env->config->nareg); @@ -201,22 +201,22 @@ static void copy_phys_from_window(CPUState *env, } -static inline unsigned windowbase_bound(unsigned a, const CPUState *env) +static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env) { return a & (env->config->nareg / 4 - 1); } -static inline unsigned windowstart_bit(unsigned a, const CPUState *env) +static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env) { return 1 << windowbase_bound(a, env); } -void xtensa_sync_window_from_phys(CPUState *env) +void xtensa_sync_window_from_phys(CPUXtensaState *env) { copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16); } -void xtensa_sync_phys_from_window(CPUState *env) +void xtensa_sync_phys_from_window(CPUXtensaState *env) { copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16); } @@ -409,7 +409,7 @@ void HELPER(advance_ccount)(uint32_t d) xtensa_advance_ccount(env, d); } -void HELPER(check_interrupts)(CPUState *env) +void HELPER(check_interrupts)(CPUXtensaState *env) { check_interrupts(env); } @@ -423,7 +423,7 @@ void HELPER(wsr_rasid)(uint32_t v) } } -static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way) +static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way) { uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; @@ -445,7 +445,7 @@ static uint32_t get_page_size(const CPUState *env, bool dtlb, uint32_t way) /*! * Get bit mask for the virtual address bits translated by the TLB way */ -uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way) +uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { bool varway56 = dtlb ? @@ -482,7 +482,7 @@ uint32_t xtensa_tlb_get_addr_mask(const CPUState *env, bool dtlb, uint32_t way) * Get bit mask for the 'VPN without index' field. * See ISA, 4.6.5.6, data format for RxTLB0 */ -static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way) +static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) { if (way < 4) { bool is32 = (dtlb ? @@ -511,7 +511,7 @@ static uint32_t get_vpn_mask(const CPUState *env, bool dtlb, uint32_t way) * Split virtual address into VPN (with index) and entry index * for the given TLB way */ -void split_tlb_entry_spec_way(const CPUState *env, uint32_t v, bool dtlb, +void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, uint32_t *vpn, uint32_t wi, uint32_t *ei) { bool varway56 = dtlb ? @@ -647,7 +647,7 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb) } } -void xtensa_tlb_set_entry(CPUState *env, bool dtlb, +void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) { xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); |